2021-01-20 19:47:18 -05:00
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Scott Shawcroft for Adafruit Industries
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "bindings/rp2pio/StateMachine.h"
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#include "common-hal/microcontroller/__init__.h"
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#include "shared-bindings/microcontroller/Pin.h"
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#include "src/rp2040/hardware_regs/include/hardware/platform_defs.h"
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#include "src/rp2_common/hardware_clocks/include/hardware/clocks.h"
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#include "src/rp2_common/hardware_dma/include/hardware/dma.h"
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#include "src/rp2_common/hardware_pio/include/hardware/pio_instructions.h"
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#include "src/rp2040/hardware_structs/include/hardware/structs/iobank0.h"
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#include "src/rp2_common/hardware_irq/include/hardware/irq.h"
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#include "lib/utils/interrupt_char.h"
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#include "py/obj.h"
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#include "py/objproperty.h"
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#include "py/runtime.h"
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// Count how many state machines are using each pin.
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STATIC uint8_t _pin_reference_count[TOTAL_GPIO_COUNT];
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STATIC uint32_t _current_program_id[NUM_PIOS][NUM_PIO_STATE_MACHINES];
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STATIC uint8_t _current_program_offset[NUM_PIOS][NUM_PIO_STATE_MACHINES];
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STATIC uint8_t _current_program_len[NUM_PIOS][NUM_PIO_STATE_MACHINES];
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STATIC bool _never_reset[NUM_PIOS][NUM_PIO_STATE_MACHINES];
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STATIC uint32_t _current_pins[NUM_PIOS];
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STATIC uint32_t _current_sm_pins[NUM_PIOS][NUM_PIO_STATE_MACHINES];
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STATIC PIO pio_instances[2] = {pio0, pio1};
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void _reset_statemachine(PIO pio, uint8_t sm, bool leave_pins) {
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uint8_t pio_index = pio_get_index(pio);
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uint32_t program_id = _current_program_id[pio_index][sm];
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if (program_id == 0) {
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return;
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}
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_current_program_id[pio_index][sm] = 0;
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bool program_in_use = false;
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for (size_t i = 0; i < NUM_PIO_STATE_MACHINES; i++) {
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if (_current_program_id[pio_index][i] == program_id) {
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program_in_use = true;
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break;
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}
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}
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if (!program_in_use) {
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uint8_t offset = _current_program_offset[pio_index][sm];
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pio_program_t program_struct = {
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.length = _current_program_len[pio_index][sm]
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};
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pio_remove_program(pio, &program_struct, offset);
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}
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uint32_t pins = _current_sm_pins[pio_index][sm];
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for (size_t pin_number = 0; pin_number < TOTAL_GPIO_COUNT; pin_number++) {
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if ((pins & (1 << pin_number)) == 0) {
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continue;
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}
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_pin_reference_count[pin_number]--;
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if (_pin_reference_count[pin_number] == 0) {
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if (!leave_pins) {
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reset_pin_number(pin_number);
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}
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_current_pins[pio_index] &= ~(1 << pin_number);
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}
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}
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_current_sm_pins[pio_index][sm] = 0;
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pio_sm_unclaim(pio, sm);
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}
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void reset_rp2pio_statemachine(void) {
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for (size_t i = 0; i < NUM_PIOS; i++) {
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PIO pio = pio_instances[i];
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for (size_t j = 0; j < NUM_PIO_STATE_MACHINES; j++) {
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if (_never_reset[i][j]) {
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continue;
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}
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_reset_statemachine(pio, j, false);
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}
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}
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for (uint8_t irq=PIO0_IRQ_0; irq <= PIO1_IRQ_1; irq++) {
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irq_handler_t int_handler = irq_get_exclusive_handler(irq);
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if (int_handler > 0) {
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irq_set_enabled (irq, false);
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irq_remove_handler(irq,int_handler);
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}
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}
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}
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STATIC uint32_t _check_pins_free(const mcu_pin_obj_t * first_pin, uint8_t pin_count, bool exclusive_pin_use) {
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uint32_t pins_we_use = 0;
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if (first_pin != NULL) {
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for (size_t i = 0; i < pin_count; i++) {
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uint8_t pin_number = first_pin->number + i;
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if (pin_number >= TOTAL_GPIO_COUNT) {
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mp_raise_ValueError(translate("Pin count too large"));
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}
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const mcu_pin_obj_t * pin = mcu_pin_global_dict_table[pin_number].value;
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if (exclusive_pin_use || _pin_reference_count[pin_number] == 0) {
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assert_pin_free(pin);
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}
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pins_we_use |= 1 << pin_number;
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}
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}
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return pins_we_use;
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}
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bool rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self,
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const uint16_t* program, size_t program_len,
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size_t frequency,
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const uint16_t* init, size_t init_len,
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const mcu_pin_obj_t * first_out_pin, uint8_t out_pin_count,
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const mcu_pin_obj_t * first_in_pin, uint8_t in_pin_count,
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const mcu_pin_obj_t * first_set_pin, uint8_t set_pin_count,
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const mcu_pin_obj_t * first_sideset_pin, uint8_t sideset_pin_count,
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uint32_t initial_pin_state, uint32_t initial_pin_direction,
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uint32_t pins_we_use, bool tx_fifo, bool rx_fifo,
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bool auto_pull, uint8_t pull_threshold, bool out_shift_right,
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bool wait_for_txstall,
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bool auto_push, uint8_t push_threshold, bool in_shift_right,
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bool claim_pins) {
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// Create a program id that isn't the pointer so we can store it without storing the original object.
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uint32_t program_id = ~((uint32_t) program);
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// Next, find a PIO and state machine to use.
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size_t pio_index = NUM_PIOS;
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uint8_t program_offset = 32;
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pio_program_t program_struct = {
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.instructions = (uint16_t*) program,
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.length = program_len,
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.origin = 0
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};
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for (size_t i = 0; i < NUM_PIOS; i++) {
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PIO pio = pio_instances[i];
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uint8_t free_count = 0;
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for (size_t j = 0; j < NUM_PIO_STATE_MACHINES; j++) {
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if (_current_program_id[i][j] == program_id &&
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_current_program_len[i][j] == program_len) {
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program_offset = _current_program_offset[i][j];
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}
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int temp_claim = pio_claim_unused_sm(pio, false);
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if (temp_claim >= 0) {
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pio_sm_unclaim(pio, temp_claim);
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free_count++;
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}
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}
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if (free_count > 0 && (program_offset < 32 || pio_can_add_program(pio, &program_struct))) {
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pio_index = i;
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if (program_offset < 32) {
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break;
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}
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}
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// Reset program offset if we weren't able to find a free state machine
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// on that PIO. (We would have broken the loop otherwise.)
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program_offset = 32;
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}
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int state_machine = -1;
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if (pio_index < NUM_PIOS) {
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PIO pio = pio_instances[pio_index];
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for (size_t i = 0; i < NUM_PIOS; i++) {
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if (i == pio_index) {
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continue;
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}
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if ((_current_pins[i] & pins_we_use) != 0) {
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// Pin in use by another PIO already.
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return false;
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}
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}
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state_machine = pio_claim_unused_sm(pio, false);
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}
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if (pio_index == NUM_PIOS || state_machine < 0 || state_machine >= NUM_PIO_STATE_MACHINES) {
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return false;
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}
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self->pio = pio_instances[pio_index];
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self->state_machine = state_machine;
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if (program_offset == 32) {
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program_offset = pio_add_program(self->pio, &program_struct);
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}
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_current_program_id[pio_index][state_machine] = program_id;
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_current_program_len[pio_index][state_machine] = program_len;
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_current_program_offset[pio_index][state_machine] = program_offset;
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_current_sm_pins[pio_index][state_machine] = pins_we_use;
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_current_pins[pio_index] |= pins_we_use;
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2021-02-23 18:50:00 -05:00
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pio_sm_set_pins_with_mask(self->pio, state_machine, initial_pin_state, pins_we_use);
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pio_sm_set_pindirs_with_mask(self->pio, state_machine, initial_pin_direction, pins_we_use);
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self->initial_pin_state = initial_pin_state;
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self->initial_pin_direction = initial_pin_direction;
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2021-01-20 19:47:18 -05:00
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for (size_t pin_number = 0; pin_number < TOTAL_GPIO_COUNT; pin_number++) {
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if ((pins_we_use & (1 << pin_number)) == 0) {
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continue;
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}
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_pin_reference_count[pin_number]++;
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const mcu_pin_obj_t * pin = mcu_pin_global_dict_table[pin_number].value;
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// Also claim the pin at the top level when we're the first to grab it.
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if (_pin_reference_count[pin_number] == 1) {
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if (claim_pins) {
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claim_pin(pin);
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}
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pio_gpio_init(self->pio, pin_number);
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}
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}
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pio_sm_config c = {0, 0, 0};
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if (frequency == 0) {
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frequency = clock_get_hz(clk_sys);
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}
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uint64_t frequency256 = ((uint64_t) clock_get_hz(clk_sys)) * 256;
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uint64_t div256 = frequency256 / frequency;
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if (frequency256 % div256 > 0) {
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div256 += 1;
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}
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self->actual_frequency = frequency256 / div256;
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sm_config_set_clkdiv_int_frac(&c, div256 / 256, div256 % 256);
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if (first_out_pin != NULL) {
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sm_config_set_out_pins(&c, first_out_pin->number, out_pin_count);
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}
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if (first_in_pin != NULL) {
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sm_config_set_in_pins(&c, first_in_pin->number);
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}
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if (first_set_pin != NULL) {
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sm_config_set_set_pins(&c, first_set_pin->number, set_pin_count);
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}
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if (first_sideset_pin != NULL) {
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sm_config_set_sideset(&c, sideset_pin_count, false /* optional */, false /* pin direction */);
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sm_config_set_sideset_pins(&c, first_sideset_pin->number);
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}
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sm_config_set_wrap(&c, program_offset, program_offset + program_len - 1);
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sm_config_set_in_shift(&c, in_shift_right, auto_push, push_threshold);
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sm_config_set_out_shift(&c, out_shift_right, auto_pull, pull_threshold);
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enum pio_fifo_join join = PIO_FIFO_JOIN_NONE;
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if (!rx_fifo) {
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join = PIO_FIFO_JOIN_TX;
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} else if (!tx_fifo) {
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join = PIO_FIFO_JOIN_RX;
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}
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if (rx_fifo) {
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self->rx_dreq = pio_get_dreq(self->pio, self->state_machine, false);
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}
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if (tx_fifo) {
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self->tx_dreq = pio_get_dreq(self->pio, self->state_machine, true);
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}
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self->in = rx_fifo;
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self->out = tx_fifo;
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self->out_shift_right = out_shift_right;
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self->in_shift_right = in_shift_right;
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self->wait_for_txstall = wait_for_txstall;
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self->init = init;
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self->init_len = init_len;
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sm_config_set_fifo_join(&c, join);
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pio_sm_init(self->pio, self->state_machine, program_offset, &c);
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common_hal_rp2pio_statemachine_run(self, init, init_len);
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common_hal_rp2pio_statemachine_set_frequency(self, frequency);
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pio_sm_set_enabled(self->pio, self->state_machine, true);
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return true;
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}
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static uint32_t mask_and_rotate(const mcu_pin_obj_t* first_pin, uint32_t bit_count, uint32_t value) {
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value = value & ((1 << bit_count) - 1);
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uint32_t shift = first_pin->number;
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return value << shift | value >> (32 - shift);
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}
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void common_hal_rp2pio_statemachine_construct(rp2pio_statemachine_obj_t *self,
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const uint16_t* program, size_t program_len,
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size_t frequency,
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const uint16_t* init, size_t init_len,
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const mcu_pin_obj_t * first_out_pin, uint8_t out_pin_count, uint32_t initial_out_pin_state, uint32_t initial_out_pin_direction,
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const mcu_pin_obj_t * first_in_pin, uint8_t in_pin_count,
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2021-02-23 18:50:00 -05:00
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const mcu_pin_obj_t * first_set_pin, uint8_t set_pin_count, uint32_t initial_set_pin_state, uint32_t initial_set_pin_direction,
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const mcu_pin_obj_t * first_sideset_pin, uint8_t sideset_pin_count, uint32_t initial_sideset_pin_state, uint32_t initial_sideset_pin_direction,
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2021-01-20 19:47:18 -05:00
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bool exclusive_pin_use,
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bool auto_pull, uint8_t pull_threshold, bool out_shift_right,
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2021-02-23 18:50:00 -05:00
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bool wait_for_txstall,
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2021-01-20 19:47:18 -05:00
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bool auto_push, uint8_t push_threshold, bool in_shift_right) {
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// First, check that all pins are free OR already in use by any PIO if exclusive_pin_use is false.
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uint32_t pins_we_use = 0;
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pins_we_use |= _check_pins_free(first_out_pin, out_pin_count, exclusive_pin_use);
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pins_we_use |= _check_pins_free(first_in_pin, in_pin_count, exclusive_pin_use);
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pins_we_use |= _check_pins_free(first_set_pin, set_pin_count, exclusive_pin_use);
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pins_we_use |= _check_pins_free(first_sideset_pin, sideset_pin_count, exclusive_pin_use);
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// Look through the program to see what we reference and make sure it was provided.
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bool tx_fifo = false;
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bool rx_fifo = false;
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bool in_loaded = false; // can be loaded in other ways besides the fifo
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bool out_loaded = false;
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bool in_used = false;
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bool out_used = false;
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for (size_t i = 0; i < program_len; i++) {
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uint16_t full_instruction = program[i];
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uint16_t instruction = full_instruction & 0xe000;
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if (instruction == 0x8000) {
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if ((full_instruction & 0xe080) == pio_instr_bits_push) {
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rx_fifo = true;
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in_loaded = true;
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} else { // pull otherwise.
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tx_fifo = true;
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out_loaded = true;
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}
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}
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if (instruction == pio_instr_bits_jmp) {
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uint16_t condition = (full_instruction & 0x00e0) >> 5;
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if (condition == 0x6) { // GPIO
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mp_raise_NotImplementedError_varg(translate("Instruction %d jumps on pin"), i);
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}
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}
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if (instruction == pio_instr_bits_wait) {
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uint16_t wait_source = (full_instruction & 0x0060) >> 5;
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uint16_t wait_index = full_instruction & 0x001f;
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if (wait_source == 0 && (pins_we_use & (1 << wait_index)) == 0) { // GPIO
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mp_raise_ValueError_varg(translate("Instruction %d uses extra pin"), i);
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}
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if (wait_source == 1) { // Input pin
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if (first_in_pin == NULL) {
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mp_raise_ValueError_varg(translate("Missing first_in_pin. Instruction %d waits based on pin"), i);
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}
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if (wait_index > in_pin_count) {
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mp_raise_ValueError_varg(translate("Instruction %d waits on input outside of count"), i);
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}
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}
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}
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if (instruction == pio_instr_bits_in) {
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uint16_t source = (full_instruction & 0x00e0) >> 5;
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uint16_t bit_count = full_instruction & 0x001f;
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if (source == 0) {
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if (first_in_pin == NULL) {
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mp_raise_ValueError_varg(translate("Missing first_in_pin. Instruction %d shifts in from pin(s)"), i);
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}
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if (bit_count > in_pin_count) {
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mp_raise_ValueError_varg(translate("Instruction %d shifts in more bits than pin count"), i);
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}
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}
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if (auto_push) {
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in_loaded = true;
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rx_fifo = true;
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}
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in_used = true;
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}
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if (instruction == pio_instr_bits_out) {
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uint16_t bit_count = full_instruction & 0x001f;
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uint16_t destination = (full_instruction & 0x00e0) >> 5;
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// Check for pins or pindirs destination.
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if (destination == 0x0 || destination == 0x4) {
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if (first_out_pin == NULL) {
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mp_raise_ValueError_varg(translate("Missing first_out_pin. Instruction %d shifts out to pin(s)"), i);
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}
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if (bit_count > out_pin_count) {
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mp_raise_ValueError_varg(translate("Instruction %d shifts out more bits than pin count"), i);
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}
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}
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if (auto_pull) {
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out_loaded = true;
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tx_fifo = true;
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}
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out_used = true;
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}
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if (instruction == pio_instr_bits_set) {
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uint16_t destination = (full_instruction & 0x00e0) >> 5;
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// Check for pins or pindirs destination.
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if ((destination == 0x00 || destination == 0x4) && first_set_pin == NULL) {
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mp_raise_ValueError_varg(translate("Missing first_set_pin. Instruction %d sets pin(s)"), i);
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}
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}
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if (instruction == pio_instr_bits_mov) {
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uint16_t source = full_instruction & 0x0007;
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uint16_t destination = (full_instruction & 0x00e0) >> 5;
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// Check for pins or pindirs destination.
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if (destination == 0x0 && first_out_pin == NULL) {
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mp_raise_ValueError_varg(translate("Missing first_out_pin. Instruction %d writes pin(s)"), i);
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}
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if (source == 0x0 && first_in_pin == NULL) {
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mp_raise_ValueError_varg(translate("Missing first_in_pin. Instruction %d reads pin(s)"), i);
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}
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if (destination == 0x6) {
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in_loaded = true;
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} else if (destination == 0x7) {
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out_loaded = true;
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}
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}
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}
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if (!in_loaded && in_used) {
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mp_raise_ValueError_varg(translate("Program does IN without loading ISR"));
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}
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if (!out_loaded && out_used) {
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mp_raise_ValueError_varg(translate("Program does OUT without loading OSR"));
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}
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2021-02-23 18:50:00 -05:00
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uint32_t initial_pin_state = mask_and_rotate(first_out_pin, out_pin_count, initial_out_pin_state);
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uint32_t initial_pin_direction = mask_and_rotate(first_out_pin, out_pin_count, initial_out_pin_direction);
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initial_set_pin_state = mask_and_rotate(first_set_pin, set_pin_count, initial_set_pin_state);
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initial_set_pin_direction = mask_and_rotate(first_set_pin, set_pin_count, initial_set_pin_direction);
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uint32_t set_out_overlap = mask_and_rotate(first_out_pin, out_pin_count, 0xffffffff) &
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mask_and_rotate(first_set_pin, set_pin_count, 0xffffffff);
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// Check that OUT and SET settings agree because we don't have a way of picking one over the other.
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if ((initial_pin_state & set_out_overlap) != (initial_set_pin_state & set_out_overlap)) {
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mp_raise_ValueError(translate("Initial set pin state conflicts with initial out pin state"));
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}
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if ((initial_pin_direction & set_out_overlap) != (initial_set_pin_direction & set_out_overlap)) {
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2021-02-26 18:03:56 -05:00
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mp_raise_ValueError(translate("Initial set pin direction conflicts with initial out pin direction"));
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2021-01-20 19:47:18 -05:00
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}
|
2021-02-23 18:50:00 -05:00
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initial_pin_state |= initial_set_pin_state;
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initial_pin_direction |= initial_set_pin_direction;
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// Sideset overrides OUT or SET so we always use its values.
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uint32_t sideset_mask = mask_and_rotate(first_sideset_pin, sideset_pin_count, 0x1f);
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initial_pin_state = (initial_pin_state & ~sideset_mask) | mask_and_rotate(first_sideset_pin, sideset_pin_count, initial_sideset_pin_state);
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initial_pin_direction = (initial_pin_direction & ~sideset_mask) | mask_and_rotate(first_sideset_pin, sideset_pin_count, initial_sideset_pin_direction);
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2021-01-20 19:47:18 -05:00
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bool ok = rp2pio_statemachine_construct(self,
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program, program_len,
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frequency,
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init, init_len,
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first_out_pin, out_pin_count,
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first_in_pin, in_pin_count,
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first_set_pin, set_pin_count,
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first_sideset_pin, sideset_pin_count,
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2021-02-23 18:50:00 -05:00
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initial_pin_state, initial_pin_direction,
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2021-01-20 19:47:18 -05:00
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pins_we_use, tx_fifo, rx_fifo,
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auto_pull, pull_threshold, out_shift_right,
|
2021-02-23 18:50:00 -05:00
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wait_for_txstall,
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2021-01-20 19:47:18 -05:00
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auto_push, push_threshold, in_shift_right,
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true /* claim pins */);
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if (!ok) {
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mp_raise_RuntimeError(translate("All state machines in use"));
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}
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}
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2021-02-23 18:50:00 -05:00
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void common_hal_rp2pio_statemachine_restart(rp2pio_statemachine_obj_t *self) {
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pio_sm_restart(self->pio, self->state_machine);
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uint8_t pio_index = pio_get_index(self->pio);
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uint32_t pins_we_use = _current_sm_pins[pio_index][self->state_machine];
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pio_sm_set_pins_with_mask(self->pio, self->state_machine, self->initial_pin_state, pins_we_use);
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pio_sm_set_pindirs_with_mask(self->pio, self->state_machine, self->initial_pin_direction, pins_we_use);
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common_hal_rp2pio_statemachine_run(self, self->init, self->init_len);
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pio_sm_set_enabled(self->pio, self->state_machine, true);
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}
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void common_hal_rp2pio_statemachine_stop(rp2pio_statemachine_obj_t *self) {
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pio_sm_set_enabled(self->pio, self->state_machine, false);
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}
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void common_hal_rp2pio_statemachine_run(rp2pio_statemachine_obj_t *self, const uint16_t *instructions, size_t len) {
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for (size_t i = 0; i < len; i++) {
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pio_sm_exec(self->pio, self->state_machine, instructions[i]);
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}
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}
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|
2021-01-20 19:47:18 -05:00
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uint32_t common_hal_rp2pio_statemachine_get_frequency(rp2pio_statemachine_obj_t* self) {
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return self->actual_frequency;
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}
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|
2021-02-23 18:50:00 -05:00
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void common_hal_rp2pio_statemachine_set_frequency(rp2pio_statemachine_obj_t* self, uint32_t frequency) {
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if (frequency == 0) {
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frequency = clock_get_hz(clk_sys);
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}
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uint64_t frequency256 = ((uint64_t) clock_get_hz(clk_sys)) * 256;
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uint64_t div256 = frequency256 / frequency;
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if (frequency256 % div256 > 0) {
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div256 += 1;
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}
|
2021-02-23 19:25:02 -05:00
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// 0 is interpreted as 0x10000 so it's valid.
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if (div256 / 256 > 0x10000 || frequency > clock_get_hz(clk_sys)) {
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mp_raise_ValueError_varg(translate("%q out of range"), MP_QSTR_frequency);
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}
|
2021-02-23 18:50:00 -05:00
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self->actual_frequency = frequency256 / div256;
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pio_sm_set_clkdiv_int_frac(self->pio, self->state_machine, div256 / 256, div256 % 256);
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// Reset the clkdiv counter in case our new TOP is lower.
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pio_sm_clkdiv_restart(self->pio, self->state_machine);
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}
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|
2021-01-20 19:47:18 -05:00
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void rp2pio_statemachine_deinit(rp2pio_statemachine_obj_t *self, bool leave_pins) {
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uint8_t sm = self->state_machine;
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uint8_t pio_index = pio_get_index(self->pio);
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_never_reset[pio_index][sm] = false;
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_reset_statemachine(self->pio, sm, leave_pins);
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self->state_machine = NUM_PIO_STATE_MACHINES;
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}
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void common_hal_rp2pio_statemachine_deinit(rp2pio_statemachine_obj_t *self) {
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rp2pio_statemachine_deinit(self, false);
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}
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void common_hal_rp2pio_statemachine_never_reset(rp2pio_statemachine_obj_t *self) {
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uint8_t sm = self->state_machine;
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uint8_t pio_index = pio_get_index(self->pio);
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|
_never_reset[pio_index][sm] = true;
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|
|
// TODO: never reset all the pins
|
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}
|
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bool common_hal_rp2pio_statemachine_deinited(rp2pio_statemachine_obj_t *self) {
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return self->state_machine == NUM_PIO_STATE_MACHINES;
|
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|
|
}
|
|
|
|
|
2021-02-23 18:50:00 -05:00
|
|
|
enum dma_channel_transfer_size _stride_to_dma_size(uint8_t stride) {
|
|
|
|
switch (stride) {
|
|
|
|
case 4:
|
|
|
|
return DMA_SIZE_32;
|
|
|
|
case 2:
|
|
|
|
return DMA_SIZE_16;
|
|
|
|
case 1:
|
|
|
|
default:
|
|
|
|
return DMA_SIZE_8;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-01-20 19:47:18 -05:00
|
|
|
static bool _transfer(rp2pio_statemachine_obj_t *self,
|
2021-02-23 18:50:00 -05:00
|
|
|
const uint8_t *data_out, size_t out_len, uint8_t out_stride_in_bytes,
|
|
|
|
uint8_t *data_in, size_t in_len, uint8_t in_stride_in_bytes) {
|
2021-01-20 19:47:18 -05:00
|
|
|
// This implementation is based on SPI but varies because the tx and rx buffers
|
|
|
|
// may be different lengths and occur at different times or speeds.
|
|
|
|
|
|
|
|
// Use DMA for large transfers if channels are available
|
|
|
|
const size_t dma_min_size_threshold = 32;
|
|
|
|
int chan_tx = -1;
|
|
|
|
int chan_rx = -1;
|
|
|
|
size_t len = MAX(out_len, in_len);
|
|
|
|
bool tx = data_out != NULL;
|
|
|
|
bool rx = data_in != NULL;
|
|
|
|
if (len >= dma_min_size_threshold) {
|
|
|
|
// Use DMA channels to service the two FIFOs
|
|
|
|
if (tx) {
|
|
|
|
chan_tx = dma_claim_unused_channel(false);
|
|
|
|
}
|
|
|
|
if (rx) {
|
|
|
|
chan_rx = dma_claim_unused_channel(false);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
volatile uint8_t* tx_destination = NULL;
|
|
|
|
const volatile uint8_t* rx_source = NULL;
|
|
|
|
if (tx) {
|
|
|
|
tx_destination = (volatile uint8_t*) &self->pio->txf[self->state_machine];
|
|
|
|
if (!self->out_shift_right) {
|
2021-02-23 18:50:00 -05:00
|
|
|
tx_destination += 4 - out_stride_in_bytes;
|
2021-01-20 19:47:18 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
if (rx) {
|
|
|
|
rx_source = (const volatile uint8_t*) &self->pio->rxf[self->state_machine];
|
2021-02-23 18:50:00 -05:00
|
|
|
if (self->in_shift_right) {
|
|
|
|
rx_source += 4 - in_stride_in_bytes;
|
2021-01-20 19:47:18 -05:00
|
|
|
}
|
|
|
|
}
|
2021-02-23 18:50:00 -05:00
|
|
|
uint32_t stall_mask = 1 << (PIO_FDEBUG_TXSTALL_LSB + self->state_machine);
|
2021-01-20 19:47:18 -05:00
|
|
|
bool use_dma = (!rx || chan_rx >= 0) && (!tx || chan_tx >= 0);
|
|
|
|
if (use_dma) {
|
|
|
|
dma_channel_config c;
|
|
|
|
uint32_t channel_mask = 0;
|
|
|
|
if (tx) {
|
|
|
|
c = dma_channel_get_default_config(chan_tx);
|
2021-02-23 18:50:00 -05:00
|
|
|
channel_config_set_transfer_data_size(&c, _stride_to_dma_size(out_stride_in_bytes));
|
2021-01-20 19:47:18 -05:00
|
|
|
channel_config_set_dreq(&c, self->tx_dreq);
|
|
|
|
channel_config_set_read_increment(&c, true);
|
|
|
|
channel_config_set_write_increment(&c, false);
|
|
|
|
dma_channel_configure(chan_tx, &c,
|
|
|
|
tx_destination,
|
|
|
|
data_out,
|
2021-02-23 18:50:00 -05:00
|
|
|
out_len / out_stride_in_bytes,
|
2021-01-20 19:47:18 -05:00
|
|
|
false);
|
|
|
|
channel_mask |= 1u << chan_tx;
|
|
|
|
}
|
|
|
|
if (rx) {
|
|
|
|
c = dma_channel_get_default_config(chan_rx);
|
2021-02-23 18:50:00 -05:00
|
|
|
channel_config_set_transfer_data_size(&c, _stride_to_dma_size(in_stride_in_bytes));
|
2021-01-20 19:47:18 -05:00
|
|
|
channel_config_set_dreq(&c, self->rx_dreq);
|
|
|
|
channel_config_set_read_increment(&c, false);
|
|
|
|
channel_config_set_write_increment(&c, true);
|
|
|
|
dma_channel_configure(chan_rx, &c,
|
|
|
|
data_in,
|
|
|
|
rx_source,
|
2021-02-23 18:50:00 -05:00
|
|
|
in_len / in_stride_in_bytes,
|
2021-01-20 19:47:18 -05:00
|
|
|
false);
|
|
|
|
channel_mask |= 1u << chan_rx;
|
|
|
|
}
|
|
|
|
|
|
|
|
dma_start_channel_mask(channel_mask);
|
|
|
|
while ((rx && dma_channel_is_busy(chan_rx)) ||
|
|
|
|
(tx && dma_channel_is_busy(chan_tx))) {
|
|
|
|
// TODO: We should idle here until we get a DMA interrupt or something else.
|
|
|
|
RUN_BACKGROUND_TASKS;
|
|
|
|
if (mp_hal_is_interrupted()) {
|
|
|
|
if (rx && dma_channel_is_busy(chan_rx)) {
|
|
|
|
dma_channel_abort(chan_rx);
|
|
|
|
}
|
|
|
|
if (tx && dma_channel_is_busy(chan_tx)) {
|
|
|
|
dma_channel_abort(chan_tx);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Clear the stall bit so we can detect when the state machine is done transmitting.
|
2021-02-23 18:50:00 -05:00
|
|
|
self->pio->fdebug = stall_mask;
|
2021-01-20 19:47:18 -05:00
|
|
|
}
|
|
|
|
|
|
|
|
// If we have claimed only one channel successfully, we should release immediately. This also
|
|
|
|
// releases the DMA after use_dma has been done.
|
|
|
|
if (chan_rx >= 0) {
|
|
|
|
dma_channel_unclaim(chan_rx);
|
|
|
|
}
|
|
|
|
if (chan_tx >= 0) {
|
|
|
|
dma_channel_unclaim(chan_tx);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!use_dma && !mp_hal_is_interrupted()) {
|
|
|
|
// Use software for small transfers, or if couldn't claim two DMA channels
|
2021-02-23 18:50:00 -05:00
|
|
|
size_t rx_remaining = in_len / in_stride_in_bytes;
|
|
|
|
size_t tx_remaining = out_len / out_stride_in_bytes;
|
2021-01-20 19:47:18 -05:00
|
|
|
|
|
|
|
while (rx_remaining || tx_remaining) {
|
2021-02-23 18:50:00 -05:00
|
|
|
while (tx_remaining && !pio_sm_is_tx_fifo_full(self->pio, self->state_machine)) {
|
|
|
|
if (out_stride_in_bytes == 1) {
|
2021-02-08 09:35:07 -05:00
|
|
|
*tx_destination = *data_out;
|
2021-02-25 16:50:49 -05:00
|
|
|
} else if (out_stride_in_bytes == 2) {
|
2021-02-23 18:50:00 -05:00
|
|
|
*((uint16_t*) tx_destination) = *((uint16_t*) data_out);
|
2021-02-25 16:50:49 -05:00
|
|
|
} else if (out_stride_in_bytes == 4) {
|
2021-02-23 18:50:00 -05:00
|
|
|
*((uint32_t*) tx_destination) = *((uint32_t*) data_out);
|
2021-02-08 09:35:07 -05:00
|
|
|
}
|
2021-02-23 18:50:00 -05:00
|
|
|
data_out += out_stride_in_bytes;
|
|
|
|
--tx_remaining;
|
|
|
|
}
|
|
|
|
while (rx_remaining && !pio_sm_is_rx_fifo_empty(self->pio, self->state_machine)) {
|
|
|
|
if (in_stride_in_bytes == 1) {
|
2021-02-08 09:35:07 -05:00
|
|
|
*data_in = (uint8_t) *rx_source;
|
2021-02-23 18:50:00 -05:00
|
|
|
} else if (in_stride_in_bytes == 2) {
|
|
|
|
*((uint16_t*) data_in) = *((uint16_t*) rx_source);
|
|
|
|
} else if (in_stride_in_bytes == 4) {
|
|
|
|
*((uint32_t*) data_in) = *((uint32_t*) rx_source);
|
2021-02-08 09:35:07 -05:00
|
|
|
}
|
2021-02-23 18:50:00 -05:00
|
|
|
data_in += in_stride_in_bytes;
|
|
|
|
--rx_remaining;
|
2021-01-20 19:47:18 -05:00
|
|
|
}
|
|
|
|
RUN_BACKGROUND_TASKS;
|
|
|
|
if (mp_hal_is_interrupted()) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// Clear the stall bit so we can detect when the state machine is done transmitting.
|
2021-02-23 18:50:00 -05:00
|
|
|
self->pio->fdebug = stall_mask;
|
2021-01-20 19:47:18 -05:00
|
|
|
}
|
|
|
|
// Wait for the state machine to finish transmitting the data we've queued
|
|
|
|
// up.
|
|
|
|
if (tx) {
|
|
|
|
while (!pio_sm_is_tx_fifo_empty(self->pio, self->state_machine) ||
|
2021-02-23 18:50:00 -05:00
|
|
|
(self->wait_for_txstall && (self->pio->fdebug & stall_mask) == 0)) {
|
2021-01-20 19:47:18 -05:00
|
|
|
RUN_BACKGROUND_TASKS;
|
2021-02-25 12:34:03 -05:00
|
|
|
if (mp_hal_is_interrupted()) {
|
|
|
|
break;
|
|
|
|
}
|
2021-01-20 19:47:18 -05:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2021-02-23 18:50:00 -05:00
|
|
|
// TODO: Provide a way around these checks in case someone wants to use the FIFO
|
|
|
|
// with manually run code.
|
|
|
|
|
|
|
|
bool common_hal_rp2pio_statemachine_write(rp2pio_statemachine_obj_t *self, const uint8_t *data, size_t len, uint8_t stride_in_bytes) {
|
2021-01-20 19:47:18 -05:00
|
|
|
if (!self->out) {
|
|
|
|
mp_raise_RuntimeError(translate("No out in program"));
|
|
|
|
}
|
2021-02-23 18:50:00 -05:00
|
|
|
return _transfer(self, data, len, stride_in_bytes, NULL, 0, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool common_hal_rp2pio_statemachine_readinto(rp2pio_statemachine_obj_t *self, uint8_t *data, size_t len, uint8_t stride_in_bytes) {
|
|
|
|
if (!self->in) {
|
|
|
|
mp_raise_RuntimeError(translate("No in in program"));
|
|
|
|
}
|
|
|
|
return _transfer(self, NULL, 0, 0, data, len, stride_in_bytes);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool common_hal_rp2pio_statemachine_write_readinto(rp2pio_statemachine_obj_t *self,
|
|
|
|
const uint8_t *data_out, size_t out_len, uint8_t out_stride_in_bytes,
|
|
|
|
uint8_t *data_in, size_t in_len, uint8_t in_stride_in_bytes) {
|
|
|
|
if (!self->in || !self->out) {
|
|
|
|
mp_raise_RuntimeError(translate("No in or out in program"));
|
|
|
|
}
|
|
|
|
return _transfer(self, data_out, out_len, out_stride_in_bytes, data_in, in_len, in_stride_in_bytes);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool common_hal_rp2pio_statemachine_get_rxstall(rp2pio_statemachine_obj_t* self) {
|
|
|
|
uint32_t stall_mask = 1 << (PIO_FDEBUG_RXSTALL_LSB + self->state_machine);
|
|
|
|
return (self->pio->fdebug & stall_mask) != 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void common_hal_rp2pio_statemachine_clear_rxfifo(rp2pio_statemachine_obj_t *self) {
|
|
|
|
uint8_t level = pio_sm_get_rx_fifo_level(self->pio, self->state_machine);
|
|
|
|
uint32_t stall_mask = 1 << (PIO_FDEBUG_RXSTALL_LSB + self->state_machine);
|
|
|
|
for (size_t i = 0; i < level; i++) {
|
|
|
|
(void) self->pio->rxf[self->state_machine];
|
|
|
|
}
|
|
|
|
self->pio->fdebug = stall_mask;
|
2021-01-20 19:47:18 -05:00
|
|
|
}
|