170 lines
4.6 KiB
C
170 lines
4.6 KiB
C
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/* Auto-generated config file hpl_dac_config.h */
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#ifndef HPL_DAC_CONFIG_H
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#define HPL_DAC_CONFIG_H
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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Basic configuration
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// <o> Reference Selection
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// <0x00=> Unbuffered external voltage reference
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// <0x01=> Voltage supply
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// <0x02=> Buffered external voltage reference
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// <0x03=> Internal bandgap reference
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// <id> dac_arch_refsel
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#ifndef CONF_DAC_REFSEL
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#define CONF_DAC_REFSEL 0
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#endif
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// <q> Differential mode
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// <i> Indicates whether the differential mode is enabled or not
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// <id> dac_arch_diff
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#ifndef CONF_DAC_DIFF
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#define CONF_DAC_DIFF 0
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#endif
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// </h>
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// <e> Advanced Configuration
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// <id> dac_advanced_settings
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#ifndef CONF_DAC_ADVANCED_CONFIG
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#define CONF_DAC_ADVANCED_CONFIG 0
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#endif
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// <q> Debug Run
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// <i> Indicate whether running when CPU is halted
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// <id> adc_arch_dbgrun
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#ifndef CONF_DAC_DBGRUN
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#define CONF_DAC_DBGRUN 1
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#endif
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// <h> Channel 0 configuration
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// <q> Left Adjusted Data
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// <i> Indicate how the data is adjusted in the Data and Data Buffer register
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// <id> dac0_arch_leftadj
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#ifndef CONF_DAC0_LEFTADJ
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#define CONF_DAC0_LEFTADJ 1
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#endif
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// <o> Current control
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// <0=> GCLK_DAC <= 1.2MHz (100kSPS)
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// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS)
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// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS)
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// <i> This defines the current in output buffer according to conversion rate
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// <id> dac0_arch_cctrl
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#ifndef CONF_DAC0_CCTRL
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#define CONF_DAC0_CCTRL 0
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#endif
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// <q> Run in standby
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// <i> Indicates whether the DAC channel will continue running in standby sleep mode or not
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// <id> dac0_arch_runstdby
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#ifndef CONF_DAC0_RUNSTDBY
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#define CONF_DAC0_RUNSTDBY 0
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#endif
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// <q> Dithering Mode
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// <i> Indicate whether dithering mode is enabled
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// <id> dac0_arch_ditrher
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#ifndef CONF_DAC0_DITHER
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#define CONF_DAC0_DITHER 0
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#endif
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// <o> Refresh period <0x00-0xFF>
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// <i> This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us
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// <id> dac0_arch_refresh
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#ifndef CONF_DAC0_REFRESH
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#define CONF_DAC0_REFRESH 2
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#endif
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// </h>
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// <h> Channel 1 configuration
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// <q> Left Adjusted Data
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// <i> Indicate how the data is adjusted in the Data and Data Buffer register
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// <id> dac1_arch_leftadj
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#ifndef CONF_DAC1_LEFTADJ
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#define CONF_DAC1_LEFTADJ 1
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#endif
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// <o> Current control
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// <0=> GCLK_DAC <= 1.2MHz (100kSPS)
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// <1=> 1.2MHz < GCLK_DAC <= 6MHz (500kSPS)
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// <2=> 6MHz < GCLK_DAC <= 12MHz (1MSPS)
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// <i> This defines the current in output buffer according to conversion rate
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// <id> dac1_arch_cctrl
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#ifndef CONF_DAC1_CCTRL
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#define CONF_DAC1_CCTRL 0
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#endif
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// <q> Run in standby
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// <i> Indicates whether the DAC channel will continue running in standby sleep mode or not
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// <id> dac1_arch_runstdby
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#ifndef CONF_DAC1_RUNSTDBY
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#define CONF_DAC1_RUNSTDBY 0
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#endif
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// <q> Dithering Mode
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// <i> Indicate whether dithering mode is enabled
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// <id> dac1_arch_ditrher
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#ifndef CONF_DAC1_DITHER
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#define CONF_DAC1_DITHER 0
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#endif
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// <o> Refresh period <0x00-0xFF>
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// <i> This defines the refresh period. If it is 0, the refresh mode is disabled, else the refresh period is: value * 500us
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// <id> dac1_arch_refresh
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#ifndef CONF_DAC1_REFRESH
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#define CONF_DAC1_REFRESH 2
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#endif
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// </h>
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// <h> Event configuration
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// <o> Inversion of DAC 0 event
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// <0=> Detection on rising edge pf the input event
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// <1=> Detection on falling edge pf the input event
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// <i> This defines the edge detection of the input event
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// <id> dac_arch_invei0
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#ifndef CONF_DAC_INVEI0
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#define CONF_DAC_INVEI0 0
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#endif
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// <q> Data Buffer of DAC 0 Empty Event Output
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// <i> Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not
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// <id> dac_arch_emptyeo_0
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#ifndef CONF_DAC_EMPTYEO0
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#define CONF_DAC_EMPTYEO0 0
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#endif
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// <q> Start Conversion Event Input DAC 0
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// <i> Indicate whether Start input event is enabled
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// <id> dac_arch_startei_0
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#ifndef CONF_DAC_STARTEI0
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#define CONF_DAC_STARTEI0 0
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#endif
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// <o> Inversion of DAC 1 event
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// <0=> Detection on rising edge pf the input event
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// <1=> Detection on falling edge pf the input event
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// <i> This defines the edge detection of the input event
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// <id> dac_arch_invei1
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#ifndef CONF_DAC_INVEI1
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#define CONF_DAC_INVEI1 0
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#endif
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// <q> Data Buffer of DAC 1 Empty Event Output
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// <i> Indicate whether Data Buffer Empty Event is enabled and generated when the Data Buffer register is empty or not
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// <id> dac_arch_emptyeo_1
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#ifndef CONF_DAC_EMPTYEO1
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#define CONF_DAC_EMPTYEO1 0
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#endif
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// <q> Start Conversion Event Input DAC 1
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// <i> Indicate whether Start input event is enabled
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// <id> dac_arch_startei_1
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#ifndef CONF_DAC_STARTEI1
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#define CONF_DAC_STARTEI1 0
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#endif
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// </h>
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// </e>
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// <<< end of configuration section >>>
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#endif // HPL_DAC_CONFIG_H
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