2021-05-30 12:18:33 -04:00
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/*
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* This file is part of the MicroPython project, http://micropython.org/
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020-2021 Damien P. George
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* Copyright (c) 2021 Robert Hammelrath
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "py/runtime.h"
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#include "py/stream.h"
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#include "py/mphal.h"
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#include "ticks.h"
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#include "fsl_common.h"
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#include "fsl_lpuart.h"
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#include "fsl_iomuxc.h"
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2022-01-01 08:00:37 -05:00
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#include CLOCK_CONFIG_H
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2021-10-20 15:24:20 -04:00
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#include "pin.h"
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2021-05-30 12:18:33 -04:00
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#define DEFAULT_UART_BAUDRATE (115200)
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#define DEFAULT_BUFFER_SIZE (256)
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#define MIN_BUFFER_SIZE (32)
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#define MAX_BUFFER_SIZE (32766)
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2023-07-30 20:01:59 -04:00
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#define UART_HWCONTROL_RTS (1)
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#define UART_HWCONTROL_CTS (2)
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#define UART_HWCONTROL_MASK (UART_HWCONTROL_RTS | UART_HWCONTROL_CTS)
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2021-05-30 12:18:33 -04:00
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#define UART_INVERT_TX (1)
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#define UART_INVERT_RX (2)
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#define UART_INVERT_MASK (UART_INVERT_TX | UART_INVERT_RX)
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typedef struct _machine_uart_obj_t {
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mp_obj_base_t base;
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struct _lpuart_handle handle;
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lpuart_config_t config;
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LPUART_Type *lpuart;
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uint16_t timeout; // timeout waiting for first char (in ms)
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uint16_t timeout_char; // timeout waiting between chars (in ms)
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uint8_t id;
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uint8_t invert;
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uint16_t tx_status;
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uint8_t *txbuf;
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uint16_t txbuf_len;
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bool new;
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} machine_uart_obj_t;
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typedef struct _iomux_table_t {
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uint32_t muxRegister;
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uint32_t muxMode;
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uint32_t inputRegister;
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uint32_t inputDaisy;
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uint32_t configRegister;
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} iomux_table_t;
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extern const mp_obj_type_t machine_uart_type;
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STATIC const uint8_t uart_index_table[] = MICROPY_HW_UART_INDEX;
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STATIC LPUART_Type *uart_base_ptr_table[] = LPUART_BASE_PTRS;
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static const iomux_table_t iomux_table_uart[] = {
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IOMUX_TABLE_UART
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};
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static const iomux_table_t iomux_table_uart_cts_rts[] = {
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IOMUX_TABLE_UART_CTS_RTS
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};
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STATIC const char *_parity_name[] = {"None", "", "0", "1"}; // Is defined as 0, 2, 3
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STATIC const char *_invert_name[] = {"None", "INV_TX", "INV_RX", "INV_TX|INV_RX"};
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STATIC const char *_flow_name[] = {"None", "RTS", "CTS", "RTS|CTS"};
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#define RX (iomux_table_uart[index + 1])
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#define TX (iomux_table_uart[index])
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#define RTS (iomux_table_uart_cts_rts[index + 1])
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#define CTS (iomux_table_uart_cts_rts[index])
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bool lpuart_set_iomux(int8_t uart) {
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int index = (uart - 1) * 2;
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if (TX.muxRegister != 0) {
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IOMUXC_SetPinMux(TX.muxRegister, TX.muxMode, TX.inputRegister, TX.inputDaisy, TX.configRegister, 0U);
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2022-01-02 07:21:06 -05:00
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IOMUXC_SetPinConfig(TX.muxRegister, TX.muxMode, TX.inputRegister, TX.inputDaisy, TX.configRegister,
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2022-03-07 10:56:14 -05:00
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pin_generate_config(PIN_PULL_UP_100K, PIN_MODE_OUT, PIN_DRIVE_6, TX.configRegister));
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2021-05-30 12:18:33 -04:00
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IOMUXC_SetPinMux(RX.muxRegister, RX.muxMode, RX.inputRegister, RX.inputDaisy, RX.configRegister, 0U);
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2022-01-02 07:21:06 -05:00
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IOMUXC_SetPinConfig(RX.muxRegister, RX.muxMode, RX.inputRegister, RX.inputDaisy, RX.configRegister,
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pin_generate_config(PIN_PULL_UP_100K, PIN_MODE_IN, PIN_DRIVE_6, RX.configRegister));
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return true;
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} else {
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return false;
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}
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}
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2023-07-30 20:01:59 -04:00
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bool lpuart_set_iomux_rts(int8_t uart) {
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MP_STATIC_ASSERT(MP_ARRAY_SIZE(iomux_table_uart) == MP_ARRAY_SIZE(iomux_table_uart_cts_rts));
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int index = (uart - 1) * 2;
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if (RTS.muxRegister != 0) {
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IOMUXC_SetPinMux(RTS.muxRegister, RTS.muxMode, RTS.inputRegister, RTS.inputDaisy, RTS.configRegister, 0U);
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IOMUXC_SetPinConfig(RTS.muxRegister, RTS.muxMode, RTS.inputRegister, RTS.inputDaisy, RTS.configRegister,
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pin_generate_config(PIN_PULL_UP_100K, PIN_MODE_OUT, PIN_DRIVE_6, RTS.configRegister));
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return true;
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} else {
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return false;
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}
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}
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bool lpuart_set_iomux_cts(int8_t uart) {
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int index = (uart - 1) * 2;
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if (CTS.muxRegister != 0) {
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IOMUXC_SetPinMux(CTS.muxRegister, CTS.muxMode, CTS.inputRegister, CTS.inputDaisy, CTS.configRegister, 0U);
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IOMUXC_SetPinConfig(CTS.muxRegister, CTS.muxMode, CTS.inputRegister, CTS.inputDaisy, CTS.configRegister,
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pin_generate_config(PIN_PULL_UP_100K, PIN_MODE_IN, PIN_DRIVE_6, CTS.configRegister));
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return true;
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} else {
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return false;
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}
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}
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2021-05-30 12:18:33 -04:00
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void LPUART_UserCallback(LPUART_Type *base, lpuart_handle_t *handle, status_t status, void *userData) {
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machine_uart_obj_t *self = userData;
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if (kStatus_LPUART_TxIdle == status) {
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self->tx_status = kStatus_LPUART_TxIdle;
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}
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if (kStatus_LPUART_RxRingBufferOverrun == status) {
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; // Ringbuffer full, deassert RTS if flow control is enabled
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}
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}
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2023-08-16 10:00:43 -04:00
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static void machine_uart_ensure_active(machine_uart_obj_t *uart) {
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if (uart->lpuart->CTRL == 0) {
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mp_raise_OSError(EIO);
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}
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}
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2021-05-30 12:18:33 -04:00
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STATIC void machine_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
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machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
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mp_printf(print, "UART(%u, baudrate=%u, bits=%u, parity=%s, stop=%u, flow=%s, "
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"rxbuf=%d, txbuf=%d, timeout=%u, timeout_char=%u, invert=%s)",
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self->id, self->config.baudRate_Bps, 8 - self->config.dataBitsCount,
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_parity_name[self->config.parityMode], self->config.stopBitCount + 1,
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2023-07-30 20:01:59 -04:00
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_flow_name[(self->config.enableTxCTS << 1) | self->config.enableRxRTS],
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2021-05-30 12:18:33 -04:00
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self->handle.rxRingBufferSize, self->txbuf_len, self->timeout, self->timeout_char,
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_invert_name[self->invert]);
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}
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STATIC mp_obj_t machine_uart_init_helper(machine_uart_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
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enum { ARG_baudrate, ARG_bits, ARG_parity, ARG_stop, ARG_flow,
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ARG_timeout, ARG_timeout_char, ARG_invert, ARG_rxbuf, ARG_txbuf};
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static const mp_arg_t allowed_args[] = {
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{ MP_QSTR_baudrate, MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_bits, MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_parity, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_INT(-1)} },
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{ MP_QSTR_stop, MP_ARG_INT, {.u_int = -1} },
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2023-07-30 20:01:59 -04:00
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{ MP_QSTR_flow, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1 } },
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2021-05-30 12:18:33 -04:00
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{ MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_timeout_char, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_invert, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_rxbuf, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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{ MP_QSTR_txbuf, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} },
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};
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// Parse args
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mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
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mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
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// Set baudrate if configured.
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if (args[ARG_baudrate].u_int > 0) {
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self->config.baudRate_Bps = args[ARG_baudrate].u_int;
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}
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// Set bits if configured.
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if (args[ARG_bits].u_int > 0) {
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self->config.dataBitsCount = 8 - args[ARG_bits].u_int;
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}
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// Set parity if configured.
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if (args[ARG_parity].u_obj != MP_OBJ_NEW_SMALL_INT(-1)) {
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if (args[ARG_parity].u_obj == mp_const_none) {
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self->config.parityMode = kLPUART_ParityDisabled;
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} else if (mp_obj_get_int(args[ARG_parity].u_obj) & 1) {
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self->config.parityMode = kLPUART_ParityOdd;
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} else {
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self->config.parityMode = kLPUART_ParityEven;
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}
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}
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// Set stop bits if configured.
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if (args[ARG_stop].u_int > 0) {
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self->config.stopBitCount = args[ARG_stop].u_int - 1;
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}
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2023-07-30 20:01:59 -04:00
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// Set flow if configured.
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if (args[ARG_flow].u_int >= 0) {
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if (args[ARG_flow].u_int & ~UART_HWCONTROL_MASK) {
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mp_raise_ValueError(MP_ERROR_TEXT("bad flow mask"));
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}
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if (args[ARG_flow].u_int & UART_HWCONTROL_RTS) {
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if (!lpuart_set_iomux_rts(uart_index_table[self->id])) {
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mp_raise_ValueError(MP_ERROR_TEXT("rts not available"));
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}
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self->config.enableRxRTS = true;
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}
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if (args[ARG_flow].u_int & UART_HWCONTROL_CTS) {
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if (!lpuart_set_iomux_cts(uart_index_table[self->id])) {
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mp_raise_ValueError(MP_ERROR_TEXT("cts not available"));
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}
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self->config.enableTxCTS = true;
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}
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}
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2021-05-30 12:18:33 -04:00
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// Set timeout if configured.
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if (args[ARG_timeout].u_int >= 0) {
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self->timeout = args[ARG_timeout].u_int;
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}
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// Set timeout_char if configured.
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if (args[ARG_timeout_char].u_int >= 0) {
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self->timeout_char = args[ARG_timeout_char].u_int;
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}
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// Set line inversion if configured.
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if (args[ARG_invert].u_int >= 0) {
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if (args[ARG_invert].u_int & ~UART_INVERT_MASK) {
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mp_raise_ValueError(MP_ERROR_TEXT("bad inversion mask"));
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}
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self->invert = args[ARG_invert].u_int;
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}
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self->tx_status = kStatus_LPUART_TxIdle;
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self->config.enableTx = true;
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self->config.enableRx = true;
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// Set the RX buffer size if configured.
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size_t rxbuf_len = DEFAULT_BUFFER_SIZE;
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if (args[ARG_rxbuf].u_int > 0) {
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rxbuf_len = args[ARG_rxbuf].u_int;
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if (rxbuf_len < MIN_BUFFER_SIZE) {
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rxbuf_len = MIN_BUFFER_SIZE;
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} else if (rxbuf_len > MAX_BUFFER_SIZE) {
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mp_raise_ValueError(MP_ERROR_TEXT("rxbuf too large"));
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}
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}
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// Set the TX buffer size if configured.
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size_t txbuf_len = DEFAULT_BUFFER_SIZE;
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if (args[ARG_txbuf].u_int > 0) {
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txbuf_len = args[ARG_txbuf].u_int;
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if (txbuf_len < MIN_BUFFER_SIZE) {
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txbuf_len = MIN_BUFFER_SIZE;
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} else if (txbuf_len > MAX_BUFFER_SIZE) {
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mp_raise_ValueError(MP_ERROR_TEXT("txbuf too large"));
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}
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}
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// Initialise the UART peripheral if any arguments given, or it was not initialised previously.
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2022-05-08 01:58:51 -04:00
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if (n_args > 0 || kw_args->used > 0 || self->new) {
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self->new = false;
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// may be obsolete
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if (self->config.baudRate_Bps == 0) {
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self->config.baudRate_Bps = DEFAULT_UART_BAUDRATE;
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}
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// Make sure timeout_char is at least as long as a whole character (13 bits to be safe).
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uint32_t min_timeout_char = 13000 / self->config.baudRate_Bps + 1;
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if (self->timeout_char < min_timeout_char) {
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self->timeout_char = min_timeout_char;
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}
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2023-08-31 02:02:32 -04:00
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#if defined(MIMXRT117x_SERIES)
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// Use the Lpuart1 clock value, which is set for All UART devices.
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LPUART_Init(self->lpuart, &self->config, CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1));
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#else
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// For baud rates < 1000000 divide the clock by 10, supporting baud rates down to 50 baud.
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if (self->config.baudRate_Bps > 1000000) {
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CLOCK_SetDiv(kCLOCK_UartDiv, 0);
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} else {
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CLOCK_SetDiv(kCLOCK_UartDiv, 9);
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}
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LPUART_Init(self->lpuart, &self->config, CLOCK_GetClockRootFreq(kCLOCK_UartClkRoot));
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#endif
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2021-05-30 12:18:33 -04:00
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LPUART_TransferCreateHandle(self->lpuart, &self->handle, LPUART_UserCallback, self);
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uint8_t *buffer = m_new(uint8_t, rxbuf_len + 1);
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LPUART_TransferStartRingBuffer(self->lpuart, &self->handle, buffer, rxbuf_len);
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self->txbuf = m_new(uint8_t, txbuf_len); // Allocate the TX buffer.
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self->txbuf_len = txbuf_len;
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// The Uart supports inverting, but not the fsl API, so it has to coded directly
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// And it has to be done after LPUART_Init.
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if (self->invert & UART_INVERT_RX) {
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LPUART_EnableRx(self->lpuart, false);
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self->lpuart->STAT |= 1 << LPUART_STAT_RXINV_SHIFT;
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LPUART_EnableRx(self->lpuart, true);
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}
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if (self->invert & UART_INVERT_TX) {
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LPUART_EnableTx(self->lpuart, false);
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self->lpuart->CTRL |= 1 << LPUART_CTRL_TXINV_SHIFT;
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LPUART_EnableTx(self->lpuart, true);
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}
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// Send long break; drop that code for a shorter break duration
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LPUART_EnableTx(self->lpuart, false);
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self->lpuart->STAT |= 1 << LPUART_STAT_BRK13_SHIFT;
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LPUART_EnableTx(self->lpuart, true);
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}
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return MP_OBJ_FROM_PTR(self);
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}
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STATIC mp_obj_t machine_uart_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
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mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true);
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// Get UART bus.
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int uart_id = mp_obj_get_int(args[0]);
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2021-11-03 10:57:48 -04:00
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if (uart_id < 0 || uart_id > MICROPY_HW_UART_NUM || uart_index_table[uart_id] == 0) {
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2021-05-30 12:18:33 -04:00
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mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("UART(%d) doesn't exist"), uart_id);
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}
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// Create the UART object and fill it with defaults.
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uint8_t uart_hw_id = uart_index_table[uart_id]; // the hw uart number 1..n
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2022-04-22 03:09:15 -04:00
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machine_uart_obj_t *self = mp_obj_malloc(machine_uart_obj_t, &machine_uart_type);
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2021-05-30 12:18:33 -04:00
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self->id = uart_id;
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self->lpuart = uart_base_ptr_table[uart_hw_id];
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self->invert = false;
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self->timeout = 1;
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self->timeout_char = 1;
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self->new = true;
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LPUART_GetDefaultConfig(&self->config);
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// Configure board-specific pin MUX based on the hardware device number.
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2021-11-03 10:57:48 -04:00
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bool uart_present = lpuart_set_iomux(uart_hw_id);
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2021-05-30 12:18:33 -04:00
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2021-11-03 10:57:48 -04:00
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if (uart_present) {
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mp_map_t kw_args;
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mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
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return machine_uart_init_helper(self, n_args - 1, args + 1, &kw_args);
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} else {
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return mp_const_none;
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}
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2021-05-30 12:18:33 -04:00
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}
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// uart.init(baud, [kwargs])
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STATIC mp_obj_t machine_uart_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
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return machine_uart_init_helper(args[0], n_args - 1, args + 1, kw_args);
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}
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MP_DEFINE_CONST_FUN_OBJ_KW(machine_uart_init_obj, 1, machine_uart_init);
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2023-08-10 11:15:47 -04:00
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// uart.deinit()
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STATIC mp_obj_t machine_uart_deinit(mp_obj_t self_in) {
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machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
2023-08-16 10:00:43 -04:00
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LPUART_SoftwareReset(self->lpuart);
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2023-08-10 11:15:47 -04:00
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return mp_const_none;
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}
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STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_uart_deinit_obj, machine_uart_deinit);
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2021-05-30 12:18:33 -04:00
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STATIC mp_obj_t machine_uart_any(mp_obj_t self_in) {
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machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
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2023-08-16 10:00:43 -04:00
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machine_uart_ensure_active(self);
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2021-05-30 12:18:33 -04:00
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size_t count = LPUART_TransferGetRxRingBufferLength(self->lpuart, &self->handle);
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return MP_OBJ_NEW_SMALL_INT(count);
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}
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STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_uart_any_obj, machine_uart_any);
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STATIC mp_obj_t machine_uart_sendbreak(mp_obj_t self_in) {
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machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
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2023-08-16 10:00:43 -04:00
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machine_uart_ensure_active(self);
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2021-05-30 12:18:33 -04:00
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self->lpuart->CTRL |= 1 << LPUART_CTRL_SBK_SHIFT; // Set SBK bit
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self->lpuart->CTRL &= ~LPUART_CTRL_SBK_MASK; // Clear SBK bit
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return mp_const_none;
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}
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STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_uart_sendbreak_obj, machine_uart_sendbreak);
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2022-08-26 09:49:59 -04:00
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STATIC mp_obj_t machine_uart_txdone(mp_obj_t self_in) {
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machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
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if (self->tx_status == kStatus_LPUART_TxIdle) {
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return mp_const_true;
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} else {
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return mp_const_false;
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}
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}
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STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_uart_txdone_obj, machine_uart_txdone);
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|
2023-08-16 10:00:43 -04:00
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// Reset all defined UARTs
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2023-08-10 11:15:47 -04:00
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void machine_uart_deinit_all(void) {
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2023-08-16 10:00:43 -04:00
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for (int i = 0; i < MICROPY_HW_UART_NUM; i++) {
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2023-08-10 11:15:47 -04:00
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if (uart_index_table[i] != 0) {
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2023-08-16 10:00:43 -04:00
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LPUART_SoftwareReset(uart_base_ptr_table[uart_index_table[i]]);
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2023-08-10 11:15:47 -04:00
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}
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}
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}
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2021-05-30 12:18:33 -04:00
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STATIC const mp_rom_map_elem_t machine_uart_locals_dict_table[] = {
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{ MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_uart_init_obj) },
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2023-08-10 11:15:47 -04:00
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{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_uart_deinit_obj) },
|
2021-05-30 12:18:33 -04:00
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{ MP_ROM_QSTR(MP_QSTR_any), MP_ROM_PTR(&machine_uart_any_obj) },
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2022-08-26 09:49:59 -04:00
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{ MP_ROM_QSTR(MP_QSTR_flush), MP_ROM_PTR(&mp_stream_flush_obj) },
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2021-05-30 12:18:33 -04:00
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{ MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_stream_read_obj) },
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{ MP_ROM_QSTR(MP_QSTR_readline), MP_ROM_PTR(&mp_stream_unbuffered_readline_obj) },
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{ MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&mp_stream_readinto_obj) },
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{ MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&mp_stream_write_obj) },
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{ MP_ROM_QSTR(MP_QSTR_sendbreak), MP_ROM_PTR(&machine_uart_sendbreak_obj) },
|
2022-08-26 09:49:59 -04:00
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{ MP_ROM_QSTR(MP_QSTR_txdone), MP_ROM_PTR(&machine_uart_txdone_obj) },
|
2021-05-30 12:18:33 -04:00
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|
2023-07-30 20:01:59 -04:00
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{ MP_ROM_QSTR(MP_QSTR_RTS), MP_ROM_INT(UART_HWCONTROL_RTS) },
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{ MP_ROM_QSTR(MP_QSTR_CTS), MP_ROM_INT(UART_HWCONTROL_CTS) },
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|
2021-05-30 12:18:33 -04:00
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{ MP_ROM_QSTR(MP_QSTR_INV_TX), MP_ROM_INT(UART_INVERT_TX) },
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{ MP_ROM_QSTR(MP_QSTR_INV_RX), MP_ROM_INT(UART_INVERT_RX) },
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};
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STATIC MP_DEFINE_CONST_DICT(machine_uart_locals_dict, machine_uart_locals_dict_table);
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STATIC mp_uint_t machine_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) {
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machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
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uint64_t t = ticks_us64() + (uint64_t)self->timeout * 1000;
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uint64_t timeout_char_us = (uint64_t)self->timeout_char * 1000;
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lpuart_transfer_t xfer;
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uint8_t *dest = buf_in;
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size_t avail;
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size_t nget;
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|
2023-08-16 10:00:43 -04:00
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machine_uart_ensure_active(self);
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|
2021-05-30 12:18:33 -04:00
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for (size_t received = 0; received < size;) {
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// Wait for the first/next character.
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while ((avail = LPUART_TransferGetRxRingBufferLength(self->lpuart, &self->handle)) <= 0) {
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if (ticks_us64() > t) { // timed out
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if (received <= 0) {
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*errcode = MP_EAGAIN;
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|
return MP_STREAM_ERROR;
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|
|
} else {
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|
|
return received;
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|
|
}
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|
|
}
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|
|
|
MICROPY_EVENT_POLL_HOOK
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|
|
}
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|
|
// Get as many bytes as possible to meet the need.
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|
nget = avail < (size - received) ? avail : size - received;
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|
xfer.data = dest + received;
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|
xfer.dataSize = nget;
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|
LPUART_TransferReceiveNonBlocking(self->lpuart, &self->handle, &xfer, NULL);
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|
|
received += nget;
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|
|
t = ticks_us64() + timeout_char_us;
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|
|
|
}
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|
|
return size;
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|
|
|
}
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|
|
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|
|
STATIC mp_uint_t machine_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) {
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machine_uart_obj_t *self = MP_OBJ_TO_PTR(self_in);
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|
|
lpuart_transfer_t xfer;
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|
|
uint64_t t;
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|
|
size_t remaining = size;
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|
|
size_t offset = 0;
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|
|
uint8_t fifo_size = FSL_FEATURE_LPUART_FIFO_SIZEn(0);
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|
|
|
2023-08-16 10:00:43 -04:00
|
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machine_uart_ensure_active(self);
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|
|
|
2021-05-30 12:18:33 -04:00
|
|
|
// First check if a previous transfer is still ongoing,
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|
|
// then wait at least the number of remaining character times.
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|
t = ticks_us64() + (uint64_t)(self->handle.txDataSize + fifo_size) * (13000000 / self->config.baudRate_Bps + 1000);
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|
|
while (self->tx_status != kStatus_LPUART_TxIdle) {
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if (ticks_us64() > t) { // timed out, hard error
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*errcode = MP_ETIMEDOUT;
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|
return MP_STREAM_ERROR;
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|
|
}
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|
|
|
MICROPY_EVENT_POLL_HOOK
|
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|
|
}
|
|
|
|
|
|
|
|
// Check if the first part has to be sent semi-blocking.
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|
|
if (size > self->txbuf_len) {
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|
|
// Send the first block.
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|
xfer.data = (uint8_t *)buf_in;
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|
|
offset = xfer.dataSize = size - self->txbuf_len;
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|
|
self->tx_status = kStatus_LPUART_TxBusy;
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|
|
LPUART_TransferSendNonBlocking(self->lpuart, &self->handle, &xfer);
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|
|
|
|
|
|
|
// Wait at least the number of character times for this chunk.
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|
|
t = ticks_us64() + (uint64_t)xfer.dataSize * (13000000 / self->config.baudRate_Bps + 1000);
|
2022-09-08 08:24:32 -04:00
|
|
|
while (self->tx_status != kStatus_LPUART_TxIdle) {
|
2021-05-30 12:18:33 -04:00
|
|
|
// Wait for the first/next character to be sent.
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|
|
if (ticks_us64() > t) { // timed out
|
|
|
|
if (self->handle.txDataSize >= size) {
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|
|
*errcode = MP_ETIMEDOUT;
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|
|
return MP_STREAM_ERROR;
|
|
|
|
} else {
|
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|
|
return size - self->handle.txDataSize;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
MICROPY_EVENT_POLL_HOOK
|
|
|
|
}
|
|
|
|
remaining = self->txbuf_len;
|
|
|
|
} else {
|
|
|
|
// The data fits into the tx buffer.
|
|
|
|
offset = 0;
|
|
|
|
remaining = size;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Send the remaining data without waiting for completion.
|
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|
|
memcpy(self->txbuf, (uint8_t *)buf_in + offset, remaining);
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|
|
|
xfer.data = self->txbuf;
|
|
|
|
xfer.dataSize = remaining;
|
|
|
|
self->tx_status = kStatus_LPUART_TxBusy;
|
|
|
|
LPUART_TransferSendNonBlocking(self->lpuart, &self->handle, &xfer);
|
|
|
|
|
|
|
|
return size;
|
|
|
|
}
|
|
|
|
|
|
|
|
STATIC mp_uint_t machine_uart_ioctl(mp_obj_t self_in, mp_uint_t request, mp_uint_t arg, int *errcode) {
|
|
|
|
machine_uart_obj_t *self = self_in;
|
|
|
|
mp_uint_t ret;
|
|
|
|
if (request == MP_STREAM_POLL) {
|
2023-08-16 10:00:43 -04:00
|
|
|
machine_uart_ensure_active(self);
|
2021-05-30 12:18:33 -04:00
|
|
|
uintptr_t flags = arg;
|
|
|
|
ret = 0;
|
|
|
|
if (flags & MP_STREAM_POLL_RD) {
|
|
|
|
uint32_t count;
|
|
|
|
count = LPUART_TransferGetRxRingBufferLength(self->lpuart, &self->handle);
|
|
|
|
if (count > 0) {
|
|
|
|
ret |= MP_STREAM_POLL_RD;
|
|
|
|
}
|
|
|
|
}
|
2022-08-18 05:36:08 -04:00
|
|
|
if ((flags & MP_STREAM_POLL_WR) && (self->tx_status == kStatus_LPUART_TxIdle)) {
|
2021-05-30 12:18:33 -04:00
|
|
|
ret |= MP_STREAM_POLL_WR;
|
|
|
|
}
|
2022-08-26 09:49:59 -04:00
|
|
|
} else if (request == MP_STREAM_FLUSH) {
|
|
|
|
// The timeout is estimated using the buffer size and the baudrate.
|
|
|
|
// Take the worst case assumptions at 13 bit symbol size times 2.
|
|
|
|
uint64_t timeout = (uint64_t)(3 + self->txbuf_len) * 13000000ll * 2 /
|
|
|
|
self->config.baudRate_Bps + ticks_us64();
|
|
|
|
|
|
|
|
do {
|
|
|
|
if (machine_uart_txdone((mp_obj_t)self) == mp_const_true) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
MICROPY_EVENT_POLL_HOOK
|
|
|
|
} while (ticks_us64() < timeout);
|
|
|
|
|
|
|
|
*errcode = MP_ETIMEDOUT;
|
|
|
|
ret = MP_STREAM_ERROR;
|
2021-05-30 12:18:33 -04:00
|
|
|
} else {
|
|
|
|
*errcode = MP_EINVAL;
|
|
|
|
ret = MP_STREAM_ERROR;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
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STATIC const mp_stream_p_t uart_stream_p = {
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.read = machine_uart_read,
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.write = machine_uart_write,
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.ioctl = machine_uart_ioctl,
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.is_text = false,
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};
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2021-07-14 00:38:38 -04:00
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MP_DEFINE_CONST_OBJ_TYPE(
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machine_uart_type,
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MP_QSTR_UART,
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2022-09-16 09:57:38 -04:00
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MP_TYPE_FLAG_ITER_IS_STREAM,
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2022-09-16 10:31:23 -04:00
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make_new, machine_uart_make_new,
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2021-07-14 00:38:38 -04:00
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print, machine_uart_print,
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protocol, &uart_stream_p,
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2022-06-24 02:27:46 -04:00
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locals_dict, &machine_uart_locals_dict
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2021-07-14 00:38:38 -04:00
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);
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