// <i> USB endpoint address is constructed by direction and endpoint number. Bit 8 of address set indicates the direction is IN. E.g., EP0x81 and EP0x01 have the same endpoint number, 1.
// <i> Reduce the value according to specific device design, to cut-off memory usage.
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> EP0 is default control endpoint, so cache must be used to be able to receive SETUP packet at any time.
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <id> usb_arch_ep0_cache
#ifndef CONF_USB_EP0_CACHE
#define CONF_USB_EP0_CACHE 64
#endif
// <h> Cache configuration EP1
// <o> Cache buffer size for EP1 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep1_cache
#ifndef CONF_USB_EP1_CACHE
#define CONF_USB_EP1_CACHE 64
#endif
// <o> Cache buffer size for EP1 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep1_I_CACHE
#ifndef CONF_USB_EP1_I_CACHE
#define CONF_USB_EP1_I_CACHE 64
#endif
// </h>
// <h> Cache configuration EP2
// <o> Cache buffer size for EP2 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep2_cache
#ifndef CONF_USB_EP2_CACHE
#define CONF_USB_EP2_CACHE 64
#endif
// <o> Cache buffer size for EP2 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep3_cache
#ifndef CONF_USB_EP3_CACHE
#define CONF_USB_EP3_CACHE 64
#endif
// <o> Cache buffer size for EP3 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep3_I_CACHE
#ifndef CONF_USB_EP3_I_CACHE
#define CONF_USB_EP3_I_CACHE 0
#endif
// </h>
// <h> Cache configuration EP4
// <o> Cache buffer size for EP4 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep4_cache
#ifndef CONF_USB_EP4_CACHE
#define CONF_USB_EP4_CACHE 64
#endif
// <o> Cache buffer size for EP4 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep4_I_CACHE
#ifndef CONF_USB_EP4_I_CACHE
#define CONF_USB_EP4_I_CACHE 0
#endif
// </h>
// <h> Cache configuration EP5
// <o> Cache buffer size for EP5 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep5_cache
#ifndef CONF_USB_EP5_CACHE
#define CONF_USB_EP5_CACHE 64
#endif
// <o> Cache buffer size for EP5 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_ep5_I_CACHE
#ifndef CONF_USB_EP5_I_CACHE
#define CONF_USB_EP5_I_CACHE 0
#endif
// </h>
// <h> Cache configuration EP6
// <o> Cache buffer size for EP6 OUT
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep6_cache
#ifndef CONF_USB_EP6_CACHE
#define CONF_USB_EP6_CACHE 64
#endif
// <o> Cache buffer size for EP6 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)
// <id> usb_arch_ep7_cache
#ifndef CONF_USB_EP7_CACHE
#define CONF_USB_EP7_CACHE 64
#endif
// <o> Cache buffer size for EP7 IN
// <i> Cache is used because the USB hardware always uses DMA which requires specific memory feature.
// <i> This cache must not be allocated if you plan to use the endpoint as control endpoint.
// <i> No cache means IN transaction not support data buffer outside of RAM, OUT transaction not support unaligned buffer and buffer size less than endpoint max packet size
// <0=> No cache
// <8=> Cached by 8 bytes buffer
// <16=> Cached by 16 bytes buffer
// <32=> Cached by 32 bytes buffer
// <64=> Cached by 64 bytes buffer
// <128=> Cached by 128 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <256=> Cached by 256 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <512=> Cached by 512 bytes buffer (HS Bulk or interrupt or isochronous EP)
// <1024=> Cached by 1024 bytes buffer (interrupt or isochronous EP)