2014-05-03 18:27:38 -04:00
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/*
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2017-06-30 03:22:17 -04:00
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* This file is part of the MicroPython project, http://micropython.org/
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2014-05-03 18:27:38 -04:00
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*
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* The MIT License (MIT)
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*
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* Copyright (c) 2013, 2014 Damien P. George
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2014-04-02 10:09:36 -04:00
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#include <stdint.h>
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#include <string.h>
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2015-01-01 16:06:20 -05:00
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#include "py/runtime.h"
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#include "py/gc.h"
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2014-04-02 10:09:36 -04:00
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#include "timer.h"
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#include "servo.h"
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2014-08-20 16:21:11 -04:00
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#include "pin.h"
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2015-10-31 13:44:20 -04:00
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#include "irq.h"
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2014-04-02 10:09:36 -04:00
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2014-05-02 11:58:15 -04:00
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/// \moduleref pyb
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/// \class Timer - periodically call a function
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///
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/// Timers can be used for a great variety of tasks. At the moment, only
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/// the simplest case is implemented: that of calling a function periodically.
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///
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/// Each timer consists of a counter that counts up at a certain rate. The rate
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/// at which it counts is the peripheral clock frequency (in Hz) divided by the
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/// timer prescaler. When the counter reaches the timer period it triggers an
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/// event, and the counter resets back to zero. By using the callback method,
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/// the timer event can call a Python function.
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///
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/// Example usage to toggle an LED at a fixed frequency:
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///
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/// tim = pyb.Timer(4) # create a timer object using timer 4
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/// tim.init(freq=2) # trigger at 2Hz
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/// tim.callback(lambda t:pyb.LED(1).toggle())
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///
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/// Further examples:
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///
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/// tim = pyb.Timer(4, freq=100) # freq in Hz
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2014-08-20 16:21:11 -04:00
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/// tim = pyb.Timer(4, prescaler=0, period=99)
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2014-05-02 11:58:15 -04:00
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/// tim.counter() # get counter (can also set)
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/// tim.prescaler(2) # set prescaler (can also get)
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2014-08-20 16:21:11 -04:00
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/// tim.period(199) # set period (can also get)
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2014-05-02 11:58:15 -04:00
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/// tim.callback(lambda t: ...) # set callback for update interrupt (t=tim instance)
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/// tim.callback(None) # clear callback
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///
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2016-01-29 17:31:56 -05:00
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/// *Note:* Timer 3 is used for fading the blue LED. Timer 5 controls
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2014-05-02 11:58:15 -04:00
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/// the servo driver, and Timer 6 is used for timed ADC/DAC reading/writing.
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/// It is recommended to use the other timers in your programs.
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2014-04-02 10:09:36 -04:00
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// The timers can be used by multiple drivers, and need a common point for
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// the interrupts to be dispatched, so they are all collected here.
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//
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// TIM3:
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// - LED 4, PWM to set the LED intensity
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//
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// TIM5:
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// - servo controller, PWM
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2014-04-21 11:48:16 -04:00
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//
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// TIM6:
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// - ADC, DAC for read_timed and write_timed
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2014-08-20 16:21:11 -04:00
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typedef enum {
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CHANNEL_MODE_PWM_NORMAL,
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CHANNEL_MODE_PWM_INVERTED,
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CHANNEL_MODE_OC_TIMING,
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CHANNEL_MODE_OC_ACTIVE,
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CHANNEL_MODE_OC_INACTIVE,
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CHANNEL_MODE_OC_TOGGLE,
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CHANNEL_MODE_OC_FORCED_ACTIVE,
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CHANNEL_MODE_OC_FORCED_INACTIVE,
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CHANNEL_MODE_IC,
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2015-03-09 04:04:12 -04:00
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CHANNEL_MODE_ENC_A,
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CHANNEL_MODE_ENC_B,
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CHANNEL_MODE_ENC_AB,
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2014-08-20 16:21:11 -04:00
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} pyb_channel_mode;
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STATIC const struct {
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qstr name;
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uint32_t oc_mode;
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2014-09-21 17:54:02 -04:00
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} channel_mode_info[] = {
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2014-08-20 16:21:11 -04:00
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{ MP_QSTR_PWM, TIM_OCMODE_PWM1 },
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{ MP_QSTR_PWM_INVERTED, TIM_OCMODE_PWM2 },
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{ MP_QSTR_OC_TIMING, TIM_OCMODE_TIMING },
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{ MP_QSTR_OC_ACTIVE, TIM_OCMODE_ACTIVE },
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{ MP_QSTR_OC_INACTIVE, TIM_OCMODE_INACTIVE },
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{ MP_QSTR_OC_TOGGLE, TIM_OCMODE_TOGGLE },
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{ MP_QSTR_OC_FORCED_ACTIVE, TIM_OCMODE_FORCED_ACTIVE },
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{ MP_QSTR_OC_FORCED_INACTIVE, TIM_OCMODE_FORCED_INACTIVE },
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{ MP_QSTR_IC, 0 },
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2015-03-09 04:04:12 -04:00
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{ MP_QSTR_ENC_A, TIM_ENCODERMODE_TI1 },
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{ MP_QSTR_ENC_B, TIM_ENCODERMODE_TI2 },
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{ MP_QSTR_ENC_AB, TIM_ENCODERMODE_TI12 },
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2014-08-20 16:21:11 -04:00
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};
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2019-03-14 07:15:35 -04:00
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enum {
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BRK_OFF,
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BRK_LOW,
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BRK_HIGH,
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};
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2014-08-20 16:21:11 -04:00
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typedef struct _pyb_timer_channel_obj_t {
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mp_obj_base_t base;
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struct _pyb_timer_obj_t *timer;
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uint8_t channel;
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uint8_t mode;
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mp_obj_t callback;
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struct _pyb_timer_channel_obj_t *next;
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} pyb_timer_channel_obj_t;
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2014-04-21 11:48:16 -04:00
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typedef struct _pyb_timer_obj_t {
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mp_obj_base_t base;
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2014-08-20 16:21:11 -04:00
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uint8_t tim_id;
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uint8_t is_32bit;
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2014-04-21 11:48:16 -04:00
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mp_obj_t callback;
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TIM_HandleTypeDef tim;
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IRQn_Type irqn;
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2014-08-20 16:21:11 -04:00
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pyb_timer_channel_obj_t *channel;
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2014-04-21 11:48:16 -04:00
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} pyb_timer_obj_t;
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2014-04-02 10:09:36 -04:00
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2014-08-20 16:21:11 -04:00
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// The following yields TIM_IT_UPDATE when channel is zero and
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// TIM_IT_CC1..TIM_IT_CC4 when channel is 1..4
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#define TIMER_IRQ_MASK(channel) (1 << (channel))
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2014-09-25 10:44:10 -04:00
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#define TIMER_CNT_MASK(self) ((self)->is_32bit ? 0xffffffff : 0xffff)
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2014-08-20 16:21:11 -04:00
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#define TIMER_CHANNEL(self) ((((self)->channel) - 1) << 2)
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2014-04-02 10:09:36 -04:00
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TIM_HandleTypeDef TIM5_Handle;
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2014-04-15 14:52:56 -04:00
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TIM_HandleTypeDef TIM6_Handle;
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2014-04-02 10:09:36 -04:00
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2015-01-07 18:38:50 -05:00
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#define PYB_TIMER_OBJ_ALL_NUM MP_ARRAY_SIZE(MP_STATE_PORT(pyb_timer_obj_all))
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2014-04-21 11:48:16 -04:00
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2014-07-02 09:09:44 -04:00
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STATIC mp_obj_t pyb_timer_deinit(mp_obj_t self_in);
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STATIC mp_obj_t pyb_timer_callback(mp_obj_t self_in, mp_obj_t callback);
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2014-08-20 16:21:11 -04:00
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STATIC mp_obj_t pyb_timer_channel_callback(mp_obj_t self_in, mp_obj_t callback);
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2014-07-02 09:09:44 -04:00
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2014-04-21 11:48:16 -04:00
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void timer_init0(void) {
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for (uint i = 0; i < PYB_TIMER_OBJ_ALL_NUM; i++) {
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2015-01-07 18:38:50 -05:00
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MP_STATE_PORT(pyb_timer_obj_all)[i] = NULL;
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2014-04-21 11:48:16 -04:00
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}
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}
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2014-07-02 09:09:44 -04:00
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// unregister all interrupt sources
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void timer_deinit(void) {
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for (uint i = 0; i < PYB_TIMER_OBJ_ALL_NUM; i++) {
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2015-01-07 18:38:50 -05:00
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pyb_timer_obj_t *tim = MP_STATE_PORT(pyb_timer_obj_all)[i];
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2014-07-02 09:09:44 -04:00
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if (tim != NULL) {
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2018-07-08 09:25:11 -04:00
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pyb_timer_deinit(MP_OBJ_FROM_PTR(tim));
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2014-07-02 09:09:44 -04:00
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}
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}
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}
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2018-02-12 23:53:39 -05:00
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#if defined(TIM5)
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2014-04-02 10:09:36 -04:00
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// TIM5 is set-up for the servo controller
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2014-04-15 14:52:56 -04:00
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// This function inits but does not start the timer
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2014-04-02 10:09:36 -04:00
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void timer_tim5_init(void) {
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// TIM5 clock enable
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2018-02-12 23:37:35 -05:00
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__HAL_RCC_TIM5_CLK_ENABLE();
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2014-04-02 10:09:36 -04:00
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// set up and enable interrupt
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2018-05-02 00:41:02 -04:00
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NVIC_SetPriority(TIM5_IRQn, IRQ_PRI_TIM5);
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2014-04-02 10:09:36 -04:00
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HAL_NVIC_EnableIRQ(TIM5_IRQn);
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// PWM clock configuration
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TIM5_Handle.Instance = TIM5;
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2014-08-20 16:21:11 -04:00
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TIM5_Handle.Init.Period = 2000 - 1; // timer cycles at 50Hz
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2014-10-04 09:36:39 -04:00
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TIM5_Handle.Init.Prescaler = (timer_get_source_freq(5) / 100000) - 1; // timer runs at 100kHz
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2014-08-20 16:21:11 -04:00
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TIM5_Handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
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2014-04-02 10:09:36 -04:00
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TIM5_Handle.Init.CounterMode = TIM_COUNTERMODE_UP;
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2014-08-20 16:21:11 -04:00
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2014-04-02 10:09:36 -04:00
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HAL_TIM_PWM_Init(&TIM5_Handle);
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}
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2018-02-12 23:53:39 -05:00
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#endif
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2014-04-02 10:09:36 -04:00
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2015-04-18 10:54:15 -04:00
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#if defined(TIM6)
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2014-04-15 14:52:56 -04:00
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// Init TIM6 with a counter-overflow at the given frequency (given in Hz)
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// TIM6 is used by the DAC and ADC for auto sampling at a given frequency
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// This function inits but does not start the timer
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2015-07-22 14:37:21 -04:00
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TIM_HandleTypeDef *timer_tim6_init(uint freq) {
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2014-04-15 14:52:56 -04:00
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// TIM6 clock enable
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2018-02-12 23:37:35 -05:00
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__HAL_RCC_TIM6_CLK_ENABLE();
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2014-04-15 14:52:56 -04:00
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// Timer runs at SystemCoreClock / 2
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// Compute the prescaler value so TIM6 triggers at freq-Hz
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2014-10-04 09:36:39 -04:00
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uint32_t period = MAX(1, timer_get_source_freq(6) / freq);
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2014-04-15 14:52:56 -04:00
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uint32_t prescaler = 1;
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while (period > 0xffff) {
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period >>= 1;
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prescaler <<= 1;
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}
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// Time base clock configuration
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TIM6_Handle.Instance = TIM6;
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TIM6_Handle.Init.Period = period - 1;
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TIM6_Handle.Init.Prescaler = prescaler - 1;
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2014-08-20 16:21:11 -04:00
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TIM6_Handle.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; // unused for TIM6
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2014-04-15 14:52:56 -04:00
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TIM6_Handle.Init.CounterMode = TIM_COUNTERMODE_UP; // unused for TIM6
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HAL_TIM_Base_Init(&TIM6_Handle);
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2015-07-22 14:37:21 -04:00
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return &TIM6_Handle;
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2014-04-15 14:52:56 -04:00
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}
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2015-04-18 10:54:15 -04:00
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#endif
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2014-04-15 14:52:56 -04:00
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2014-04-02 10:09:36 -04:00
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// Interrupt dispatch
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void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
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2017-07-14 03:41:43 -04:00
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#if MICROPY_HW_ENABLE_SERVO
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2015-12-04 09:07:15 -05:00
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if (htim == &TIM5_Handle) {
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2014-04-02 10:09:36 -04:00
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servo_timer_irq_callback();
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}
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2017-07-14 03:41:43 -04:00
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#endif
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2014-04-02 10:09:36 -04:00
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}
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2014-10-04 09:36:39 -04:00
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// Get the frequency (in Hz) of the source clock for the given timer.
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// On STM32F405/407/415/417 there are 2 cases for how the clock freq is set.
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// If the APB prescaler is 1, then the timer clock is equal to its respective
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// APB clock. Otherwise (APB prescaler > 1) the timer clock is twice its
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// respective APB clock. See DM00031020 Rev 4, page 115.
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2016-01-29 17:44:43 -05:00
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uint32_t timer_get_source_freq(uint32_t tim_id) {
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2023-03-22 01:38:49 -04:00
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#if defined(STM32H5)
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uint32_t source, ppre;
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if ((2 <= tim_id && tim_id <= 7) || (12 <= tim_id && tim_id <= 14)) {
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// TIM{2-7,12-14} are on APB1
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source = HAL_RCC_GetPCLK1Freq();
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ppre = (RCC->CFGR2 >> RCC_CFGR2_PPRE1_Pos) & 7;
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} else {
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// TIM{1,8,15-17} are on APB2
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source = HAL_RCC_GetPCLK2Freq();
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ppre = (RCC->CFGR2 >> RCC_CFGR2_PPRE2_Pos) & 7;
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}
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if (RCC->CFGR1 & RCC_CFGR1_TIMPRE) {
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if (ppre == 0 || ppre == 4 || ppre == 5) {
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// PPREx divider is 1, 2 or 4.
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return 2 * source;
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} else {
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return 4 * source;
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}
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} else {
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if (ppre == 0 || ppre == 4) {
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// PPREx divider is 1 or 2.
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return HAL_RCC_GetHCLKFreq();
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} else {
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return 2 * source;
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}
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}
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#else
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2018-05-27 21:57:17 -04:00
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uint32_t source, clk_div;
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2014-10-04 09:36:39 -04:00
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if (tim_id == 1 || (8 <= tim_id && tim_id <= 11)) {
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// TIM{1,8,9,10,11} are on APB2
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2022-02-12 15:36:58 -05:00
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#if defined(STM32F0) || defined(STM32G0)
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2018-05-28 04:10:53 -04:00
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source = HAL_RCC_GetPCLK1Freq();
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clk_div = RCC->CFGR & RCC_CFGR_PPRE;
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2021-09-15 09:08:16 -04:00
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#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ)
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source = HAL_RCC_GetPCLK2Freq();
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|
|
clk_div = RCC->CDCFGR2 & RCC_CDCFGR2_CDPPRE2;
|
2018-05-28 04:10:53 -04:00
|
|
|
#elif defined(STM32H7)
|
2014-10-04 09:36:39 -04:00
|
|
|
source = HAL_RCC_GetPCLK2Freq();
|
2018-05-27 21:57:17 -04:00
|
|
|
clk_div = RCC->D2CFGR & RCC_D2CFGR_D2PPRE2;
|
|
|
|
#else
|
2018-05-28 04:10:53 -04:00
|
|
|
source = HAL_RCC_GetPCLK2Freq();
|
2018-05-27 21:57:17 -04:00
|
|
|
clk_div = RCC->CFGR & RCC_CFGR_PPRE2;
|
|
|
|
#endif
|
2014-10-04 09:36:39 -04:00
|
|
|
} else {
|
|
|
|
// TIM{2,3,4,5,6,7,12,13,14} are on APB1
|
|
|
|
source = HAL_RCC_GetPCLK1Freq();
|
2022-02-12 15:36:58 -05:00
|
|
|
#if defined(STM32F0) || defined(STM32G0)
|
2018-05-28 04:10:53 -04:00
|
|
|
clk_div = RCC->CFGR & RCC_CFGR_PPRE;
|
2021-09-15 09:08:16 -04:00
|
|
|
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ)
|
|
|
|
clk_div = RCC->CDCFGR1 & RCC_CDCFGR2_CDPPRE1;
|
2018-05-28 04:10:53 -04:00
|
|
|
#elif defined(STM32H7)
|
2018-05-27 21:57:17 -04:00
|
|
|
clk_div = RCC->D2CFGR & RCC_D2CFGR_D2PPRE1;
|
|
|
|
#else
|
|
|
|
clk_div = RCC->CFGR & RCC_CFGR_PPRE1;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
if (clk_div != 0) {
|
|
|
|
// APB prescaler for this timer is > 1
|
|
|
|
source *= 2;
|
2014-10-04 09:36:39 -04:00
|
|
|
}
|
|
|
|
return source;
|
2023-03-22 01:38:49 -04:00
|
|
|
|
|
|
|
#endif
|
2014-10-04 09:36:39 -04:00
|
|
|
}
|
|
|
|
|
2014-04-21 11:48:16 -04:00
|
|
|
/******************************************************************************/
|
2017-06-30 03:22:17 -04:00
|
|
|
/* MicroPython bindings */
|
2014-04-21 11:48:16 -04:00
|
|
|
|
2014-09-21 17:54:02 -04:00
|
|
|
STATIC const mp_obj_type_t pyb_timer_channel_type;
|
|
|
|
|
2014-09-26 12:04:05 -04:00
|
|
|
// This is the largest value that we can multiply by 100 and have the result
|
|
|
|
// fit in a uint32_t.
|
|
|
|
#define MAX_PERIOD_DIV_100 42949672
|
|
|
|
|
2014-10-04 09:36:39 -04:00
|
|
|
// computes prescaler and period so TIM triggers at freq-Hz
|
|
|
|
STATIC uint32_t compute_prescaler_period_from_freq(pyb_timer_obj_t *self, mp_obj_t freq_in, uint32_t *period_out) {
|
|
|
|
uint32_t source_freq = timer_get_source_freq(self->tim_id);
|
|
|
|
uint32_t prescaler = 1;
|
|
|
|
uint32_t period;
|
|
|
|
if (0) {
|
|
|
|
#if MICROPY_PY_BUILTINS_FLOAT
|
2019-01-30 06:05:48 -05:00
|
|
|
} else if (mp_obj_is_type(freq_in, &mp_type_float)) {
|
2020-03-31 08:48:08 -04:00
|
|
|
float freq = mp_obj_get_float_to_f(freq_in);
|
2014-10-04 09:36:39 -04:00
|
|
|
if (freq <= 0) {
|
|
|
|
goto bad_freq;
|
|
|
|
}
|
2014-10-04 09:59:35 -04:00
|
|
|
while (freq < 1 && prescaler < 6553) {
|
|
|
|
prescaler *= 10;
|
2020-04-13 14:56:31 -04:00
|
|
|
freq *= 10.0f;
|
2014-10-04 09:59:35 -04:00
|
|
|
}
|
2020-04-13 14:56:31 -04:00
|
|
|
period = (uint32_t)((float)source_freq / freq);
|
2014-10-04 09:36:39 -04:00
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
mp_int_t freq = mp_obj_get_int(freq_in);
|
|
|
|
if (freq <= 0) {
|
|
|
|
goto bad_freq;
|
|
|
|
bad_freq:
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("must have positive freq"));
|
2014-10-04 09:36:39 -04:00
|
|
|
}
|
2014-10-04 09:59:35 -04:00
|
|
|
period = source_freq / freq;
|
2014-10-04 09:36:39 -04:00
|
|
|
}
|
2014-10-04 09:59:35 -04:00
|
|
|
period = MAX(1, period);
|
2014-10-04 09:36:39 -04:00
|
|
|
while (period > TIMER_CNT_MASK(self)) {
|
2014-10-04 09:59:35 -04:00
|
|
|
// if we can divide exactly, do that first
|
|
|
|
if (period % 5 == 0) {
|
|
|
|
prescaler *= 5;
|
|
|
|
period /= 5;
|
|
|
|
} else if (period % 3 == 0) {
|
|
|
|
prescaler *= 3;
|
|
|
|
period /= 3;
|
|
|
|
} else {
|
|
|
|
// may not divide exactly, but loses minimal precision
|
|
|
|
prescaler <<= 1;
|
|
|
|
period >>= 1;
|
|
|
|
}
|
2014-10-04 09:36:39 -04:00
|
|
|
}
|
|
|
|
*period_out = (period - 1) & TIMER_CNT_MASK(self);
|
|
|
|
return (prescaler - 1) & 0xffff;
|
|
|
|
}
|
|
|
|
|
2018-07-03 21:56:36 -04:00
|
|
|
// computes prescaler and period so TIM triggers with a period of t_num/t_den seconds
|
|
|
|
STATIC uint32_t compute_prescaler_period_from_t(pyb_timer_obj_t *self, int32_t t_num, int32_t t_den, uint32_t *period_out) {
|
|
|
|
uint32_t source_freq = timer_get_source_freq(self->tim_id);
|
|
|
|
if (t_num <= 0 || t_den <= 0) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("must have positive freq"));
|
2018-07-03 21:56:36 -04:00
|
|
|
}
|
|
|
|
uint64_t period = (uint64_t)source_freq * (uint64_t)t_num / (uint64_t)t_den;
|
|
|
|
uint32_t prescaler = 1;
|
|
|
|
while (period > TIMER_CNT_MASK(self)) {
|
|
|
|
// if we can divide exactly, and without prescaler overflow, do that first
|
|
|
|
if (prescaler <= 13107 && period % 5 == 0) {
|
|
|
|
prescaler *= 5;
|
|
|
|
period /= 5;
|
|
|
|
} else if (prescaler <= 21845 && period % 3 == 0) {
|
|
|
|
prescaler *= 3;
|
|
|
|
period /= 3;
|
|
|
|
} else {
|
|
|
|
// may not divide exactly, but loses minimal precision
|
|
|
|
uint32_t period_lsb = period & 1;
|
|
|
|
prescaler <<= 1;
|
|
|
|
period >>= 1;
|
|
|
|
if (period < prescaler) {
|
|
|
|
// round division up
|
|
|
|
prescaler |= period_lsb;
|
|
|
|
}
|
|
|
|
if (prescaler > 0x10000) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("period too large"));
|
2018-07-03 21:56:36 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
*period_out = (period - 1) & TIMER_CNT_MASK(self);
|
|
|
|
return (prescaler - 1) & 0xffff;
|
|
|
|
}
|
|
|
|
|
2014-09-26 12:04:05 -04:00
|
|
|
// Helper function for determining the period used for calculating percent
|
|
|
|
STATIC uint32_t compute_period(pyb_timer_obj_t *self) {
|
|
|
|
// In center mode, compare == period corresponds to 100%
|
|
|
|
// In edge mode, compare == (period + 1) corresponds to 100%
|
2018-02-12 23:37:35 -05:00
|
|
|
uint32_t period = (__HAL_TIM_GET_AUTORELOAD(&self->tim) & TIMER_CNT_MASK(self));
|
2014-09-26 12:04:05 -04:00
|
|
|
if (period != 0xffffffff) {
|
|
|
|
if (self->tim.Init.CounterMode == TIM_COUNTERMODE_UP ||
|
|
|
|
self->tim.Init.CounterMode == TIM_COUNTERMODE_DOWN) {
|
|
|
|
// Edge mode
|
|
|
|
period++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return period;
|
|
|
|
}
|
|
|
|
|
2014-09-25 10:44:10 -04:00
|
|
|
// Helper function to compute PWM value from timer period and percent value.
|
2014-09-26 12:04:05 -04:00
|
|
|
// 'percent_in' can be an int or a float between 0 and 100 (out of range
|
|
|
|
// values are clamped).
|
|
|
|
STATIC uint32_t compute_pwm_value_from_percent(uint32_t period, mp_obj_t percent_in) {
|
2014-09-25 10:44:10 -04:00
|
|
|
uint32_t cmp;
|
|
|
|
if (0) {
|
|
|
|
#if MICROPY_PY_BUILTINS_FLOAT
|
2019-01-30 06:05:48 -05:00
|
|
|
} else if (mp_obj_is_type(percent_in, &mp_type_float)) {
|
2015-12-09 12:39:34 -05:00
|
|
|
mp_float_t percent = mp_obj_get_float(percent_in);
|
2014-09-26 12:04:05 -04:00
|
|
|
if (percent <= 0.0) {
|
|
|
|
cmp = 0;
|
|
|
|
} else if (percent >= 100.0) {
|
|
|
|
cmp = period;
|
|
|
|
} else {
|
2020-04-13 14:56:31 -04:00
|
|
|
cmp = (uint32_t)(percent / MICROPY_FLOAT_CONST(100.0) * ((mp_float_t)period));
|
2014-09-26 12:04:05 -04:00
|
|
|
}
|
2014-09-25 10:44:10 -04:00
|
|
|
#endif
|
|
|
|
} else {
|
|
|
|
// For integer arithmetic, if period is large and 100*period will
|
|
|
|
// overflow, then divide period before multiplying by cmp. Otherwise
|
|
|
|
// do it the other way round to retain precision.
|
2014-09-26 12:04:05 -04:00
|
|
|
mp_int_t percent = mp_obj_get_int(percent_in);
|
|
|
|
if (percent <= 0) {
|
|
|
|
cmp = 0;
|
|
|
|
} else if (percent >= 100) {
|
|
|
|
cmp = period;
|
|
|
|
} else if (period > MAX_PERIOD_DIV_100) {
|
|
|
|
cmp = (uint32_t)percent * (period / 100);
|
2014-09-25 10:44:10 -04:00
|
|
|
} else {
|
2014-09-26 12:04:05 -04:00
|
|
|
cmp = ((uint32_t)percent * period) / 100;
|
2014-09-25 10:44:10 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return cmp;
|
|
|
|
}
|
|
|
|
|
2014-09-26 12:04:05 -04:00
|
|
|
// Helper function to compute percentage from timer perion and PWM value.
|
|
|
|
STATIC mp_obj_t compute_percent_from_pwm_value(uint32_t period, uint32_t cmp) {
|
|
|
|
#if MICROPY_PY_BUILTINS_FLOAT
|
2015-12-09 12:39:34 -05:00
|
|
|
mp_float_t percent;
|
2014-09-29 09:15:01 -04:00
|
|
|
if (cmp >= period) {
|
2014-09-26 12:04:05 -04:00
|
|
|
percent = 100.0;
|
|
|
|
} else {
|
2015-12-09 12:39:34 -05:00
|
|
|
percent = (mp_float_t)cmp * 100.0 / ((mp_float_t)period);
|
2014-09-26 12:04:05 -04:00
|
|
|
}
|
|
|
|
return mp_obj_new_float(percent);
|
|
|
|
#else
|
|
|
|
mp_int_t percent;
|
2014-09-29 09:15:01 -04:00
|
|
|
if (cmp >= period) {
|
2014-09-26 12:04:05 -04:00
|
|
|
percent = 100;
|
2014-09-29 09:15:01 -04:00
|
|
|
} else if (cmp > MAX_PERIOD_DIV_100) {
|
|
|
|
percent = cmp / (period / 100);
|
2014-09-26 12:04:05 -04:00
|
|
|
} else {
|
|
|
|
percent = cmp * 100 / period;
|
|
|
|
}
|
|
|
|
return mp_obj_new_int(percent);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2022-09-19 04:56:31 -04:00
|
|
|
#if !defined(STM32L0) && !defined(STM32L1)
|
2019-07-05 03:24:59 -04:00
|
|
|
|
2014-10-10 12:56:41 -04:00
|
|
|
// Computes the 8-bit value for the DTG field in the BDTR register.
|
|
|
|
//
|
|
|
|
// 1 tick = 1 count of the timer's clock (source_freq) divided by div.
|
|
|
|
// 0-128 ticks in increments of 1
|
|
|
|
// 128-256 ticks in increments of 2
|
|
|
|
// 256-512 ticks in increments of 8
|
|
|
|
// 512-1008 ticks in increments of 16
|
|
|
|
STATIC uint32_t compute_dtg_from_ticks(mp_int_t ticks) {
|
|
|
|
if (ticks <= 0) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if (ticks < 128) {
|
|
|
|
return ticks;
|
|
|
|
}
|
|
|
|
if (ticks < 256) {
|
|
|
|
return 0x80 | ((ticks - 128) / 2);
|
|
|
|
}
|
|
|
|
if (ticks < 512) {
|
|
|
|
return 0xC0 | ((ticks - 256) / 8);
|
|
|
|
}
|
|
|
|
if (ticks < 1008) {
|
|
|
|
return 0xE0 | ((ticks - 512) / 16);
|
|
|
|
}
|
|
|
|
return 0xFF;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Given the 8-bit value stored in the DTG field of the BDTR register, compute
|
|
|
|
// the number of ticks.
|
|
|
|
STATIC mp_int_t compute_ticks_from_dtg(uint32_t dtg) {
|
|
|
|
if ((dtg & 0x80) == 0) {
|
|
|
|
return dtg & 0x7F;
|
|
|
|
}
|
|
|
|
if ((dtg & 0xC0) == 0x80) {
|
|
|
|
return 128 + ((dtg & 0x3F) * 2);
|
|
|
|
}
|
|
|
|
if ((dtg & 0xE0) == 0xC0) {
|
|
|
|
return 256 + ((dtg & 0x1F) * 8);
|
|
|
|
}
|
|
|
|
return 512 + ((dtg & 0x1F) * 16);
|
|
|
|
}
|
|
|
|
|
2019-03-14 07:15:35 -04:00
|
|
|
STATIC void config_deadtime(pyb_timer_obj_t *self, mp_int_t ticks, mp_int_t brk) {
|
2023-08-15 01:29:15 -04:00
|
|
|
TIM_BreakDeadTimeConfigTypeDef deadTimeConfig = {0};
|
2014-10-10 12:56:41 -04:00
|
|
|
deadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
|
|
|
|
deadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
|
|
|
|
deadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
|
|
|
|
deadTimeConfig.DeadTime = compute_dtg_from_ticks(ticks);
|
2019-03-14 07:15:35 -04:00
|
|
|
deadTimeConfig.BreakState = brk == BRK_OFF ? TIM_BREAK_DISABLE : TIM_BREAK_ENABLE;
|
|
|
|
deadTimeConfig.BreakPolarity = brk == BRK_LOW ? TIM_BREAKPOLARITY_LOW : TIM_BREAKPOLARITY_HIGH;
|
2022-02-12 15:36:58 -05:00
|
|
|
#if defined(STM32F7) || defined(STM32G0) || defined(STM32G4) || defined(STM32H7) || defined(STM32L4) || defined(STM32WB)
|
2019-04-14 21:41:03 -04:00
|
|
|
deadTimeConfig.BreakFilter = 0;
|
|
|
|
deadTimeConfig.Break2State = TIM_BREAK_DISABLE;
|
|
|
|
deadTimeConfig.Break2Polarity = TIM_BREAKPOLARITY_LOW;
|
|
|
|
deadTimeConfig.Break2Filter = 0;
|
|
|
|
#endif
|
2014-10-10 12:56:41 -04:00
|
|
|
deadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
|
|
|
|
HAL_TIMEx_ConfigBreakDeadTime(&self->tim, &deadTimeConfig);
|
|
|
|
}
|
|
|
|
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
|
|
|
|
2015-07-21 18:37:45 -04:00
|
|
|
TIM_HandleTypeDef *pyb_timer_get_handle(mp_obj_t timer) {
|
2015-07-22 14:37:21 -04:00
|
|
|
if (mp_obj_get_type(timer) != &pyb_timer_type) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("need a Timer object"));
|
2015-07-22 14:37:21 -04:00
|
|
|
}
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_obj_t *self = MP_OBJ_TO_PTR(timer);
|
2015-07-21 18:37:45 -04:00
|
|
|
return &self->tim;
|
|
|
|
}
|
|
|
|
|
2015-04-09 18:56:15 -04:00
|
|
|
STATIC void pyb_timer_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
2014-04-21 11:48:16 -04:00
|
|
|
|
|
|
|
if (self->tim.State == HAL_TIM_STATE_RESET) {
|
2015-04-09 18:56:15 -04:00
|
|
|
mp_printf(print, "Timer(%u)", self->tim_id);
|
2014-04-21 11:48:16 -04:00
|
|
|
} else {
|
2014-10-04 09:36:39 -04:00
|
|
|
uint32_t prescaler = self->tim.Instance->PSC & 0xffff;
|
2018-02-12 23:37:35 -05:00
|
|
|
uint32_t period = __HAL_TIM_GET_AUTORELOAD(&self->tim) & TIMER_CNT_MASK(self);
|
2014-10-04 09:36:39 -04:00
|
|
|
// for efficiency, we compute and print freq as an int (not a float)
|
|
|
|
uint32_t freq = timer_get_source_freq(self->tim_id) / ((prescaler + 1) * (period + 1));
|
2015-04-09 18:56:15 -04:00
|
|
|
mp_printf(print, "Timer(%u, freq=%u, prescaler=%u, period=%u, mode=%s, div=%u",
|
2014-04-21 11:48:16 -04:00
|
|
|
self->tim_id,
|
2014-10-04 09:36:39 -04:00
|
|
|
freq,
|
|
|
|
prescaler,
|
|
|
|
period,
|
2014-08-20 16:21:11 -04:00
|
|
|
self->tim.Init.CounterMode == TIM_COUNTERMODE_UP ? "UP" :
|
|
|
|
self->tim.Init.CounterMode == TIM_COUNTERMODE_DOWN ? "DOWN" : "CENTER",
|
|
|
|
self->tim.Init.ClockDivision == TIM_CLOCKDIVISION_DIV4 ? 4 :
|
|
|
|
self->tim.Init.ClockDivision == TIM_CLOCKDIVISION_DIV2 ? 2 : 1);
|
2016-03-22 12:07:43 -04:00
|
|
|
|
2022-09-19 04:56:31 -04:00
|
|
|
#if !defined(STM32L0) && !defined(STM32L1)
|
2016-03-22 12:07:43 -04:00
|
|
|
#if defined(IS_TIM_ADVANCED_INSTANCE)
|
|
|
|
if (IS_TIM_ADVANCED_INSTANCE(self->tim.Instance))
|
|
|
|
#elif defined(IS_TIM_BREAK_INSTANCE)
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(self->tim.Instance))
|
|
|
|
#else
|
|
|
|
if (0)
|
|
|
|
#endif
|
|
|
|
{
|
2015-04-09 18:56:15 -04:00
|
|
|
mp_printf(print, ", deadtime=%u",
|
|
|
|
compute_ticks_from_dtg(self->tim.Instance->BDTR & TIM_BDTR_DTG));
|
2019-03-14 07:15:35 -04:00
|
|
|
if ((self->tim.Instance->BDTR & TIM_BDTR_BKE) == TIM_BDTR_BKE) {
|
|
|
|
mp_printf(print, ", brk=%s",
|
|
|
|
((self->tim.Instance->BDTR & TIM_BDTR_BKP) == TIM_BDTR_BKP) ? "BRK_HIGH" : "BRK_LOW");
|
|
|
|
} else {
|
|
|
|
mp_printf(print, ", brk=BRK_OFF");
|
|
|
|
}
|
2014-10-10 12:56:41 -04:00
|
|
|
}
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2015-04-09 18:56:15 -04:00
|
|
|
mp_print_str(print, ")");
|
2014-04-21 11:48:16 -04:00
|
|
|
}
|
|
|
|
}
|
2014-04-02 10:09:36 -04:00
|
|
|
|
2014-05-02 11:58:15 -04:00
|
|
|
/// \method init(*, freq, prescaler, period)
|
|
|
|
/// Initialise the timer. Initialisation must be either by frequency (in Hz)
|
|
|
|
/// or by prescaler and period:
|
|
|
|
///
|
|
|
|
/// tim.init(freq=100) # set the timer to trigger at 100Hz
|
2014-08-20 16:21:11 -04:00
|
|
|
/// tim.init(prescaler=83, period=999) # set the prescaler and period directly
|
|
|
|
///
|
|
|
|
/// Keyword arguments:
|
|
|
|
///
|
|
|
|
/// - `freq` - specifies the periodic frequency of the timer. You might also
|
|
|
|
/// view this as the frequency with which the timer goes through
|
|
|
|
/// one complete cycle.
|
|
|
|
///
|
|
|
|
/// - `prescaler` [0-0xffff] - specifies the value to be loaded into the
|
|
|
|
/// timer's Prescaler Register (PSC). The timer clock source is divided by
|
|
|
|
/// (`prescaler + 1`) to arrive at the timer clock. Timers 2-7 and 12-14
|
|
|
|
/// have a clock source of 84 MHz (pyb.freq()[2] * 2), and Timers 1, and 8-11
|
|
|
|
/// have a clock source of 168 MHz (pyb.freq()[3] * 2).
|
|
|
|
///
|
|
|
|
/// - `period` [0-0xffff] for timers 1, 3, 4, and 6-15. [0-0x3fffffff] for timers 2 & 5.
|
|
|
|
/// Specifies the value to be loaded into the timer's AutoReload
|
|
|
|
/// Register (ARR). This determines the period of the timer (i.e. when the
|
|
|
|
/// counter cycles). The timer counter will roll-over after `period + 1`
|
|
|
|
/// timer clock cycles.
|
|
|
|
///
|
|
|
|
/// - `mode` can be one of:
|
|
|
|
/// - `Timer.UP` - configures the timer to count from 0 to ARR (default)
|
|
|
|
/// - `Timer.DOWN` - configures the timer to count from ARR down to 0.
|
|
|
|
/// - `Timer.CENTER` - confgures the timer to count from 0 to ARR and
|
|
|
|
/// then back down to 0.
|
|
|
|
///
|
|
|
|
/// - `div` can be one of 1, 2, or 4. Divides the timer clock to determine
|
|
|
|
/// the sampling clock used by the digital filters.
|
|
|
|
///
|
|
|
|
/// - `callback` - as per Timer.callback()
|
|
|
|
///
|
2014-10-10 12:56:41 -04:00
|
|
|
/// - `deadtime` - specifies the amount of "dead" or inactive time between
|
|
|
|
/// transitions on complimentary channels (both channels will be inactive)
|
|
|
|
/// for this time). `deadtime` may be an integer between 0 and 1008, with
|
|
|
|
/// the following restrictions: 0-128 in steps of 1. 128-256 in steps of
|
|
|
|
/// 2, 256-512 in steps of 8, and 512-1008 in steps of 16. `deadime`
|
|
|
|
/// measures ticks of `source_freq` divided by `div` clock ticks.
|
|
|
|
/// `deadtime` is only available on timers 1 and 8.
|
|
|
|
///
|
2019-03-14 07:15:35 -04:00
|
|
|
/// - `brk` - specifies if the break mode is used to kill the output of
|
|
|
|
/// the PWM when the BRK_IN input is asserted. The polarity set how the
|
|
|
|
/// BRK_IN input is triggered. It can be set to `BRK_OFF`, `BRK_LOW`
|
|
|
|
/// and `BRK_HIGH`.
|
|
|
|
///
|
|
|
|
///
|
2014-08-20 16:21:11 -04:00
|
|
|
/// You must either specify freq or both of period and prescaler.
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_init_helper(pyb_timer_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
|
2019-03-14 07:15:35 -04:00
|
|
|
enum { ARG_freq, ARG_prescaler, ARG_period, ARG_tick_hz, ARG_mode, ARG_div, ARG_callback, ARG_deadtime, ARG_brk };
|
2014-10-04 09:36:39 -04:00
|
|
|
static const mp_arg_t allowed_args[] = {
|
2019-12-15 23:40:05 -05:00
|
|
|
{ MP_QSTR_freq, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
|
2014-10-04 09:36:39 -04:00
|
|
|
{ MP_QSTR_prescaler, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0xffffffff} },
|
|
|
|
{ MP_QSTR_period, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0xffffffff} },
|
2018-07-03 21:56:36 -04:00
|
|
|
{ MP_QSTR_tick_hz, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} },
|
2014-10-04 09:36:39 -04:00
|
|
|
{ MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = TIM_COUNTERMODE_UP} },
|
|
|
|
{ MP_QSTR_div, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1} },
|
2019-12-15 23:40:05 -05:00
|
|
|
{ MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
|
2014-10-10 12:56:41 -04:00
|
|
|
{ MP_QSTR_deadtime, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
|
2019-03-14 07:15:35 -04:00
|
|
|
{ MP_QSTR_brk, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = BRK_OFF} },
|
2014-10-04 09:36:39 -04:00
|
|
|
};
|
2014-04-02 10:09:36 -04:00
|
|
|
|
2014-04-21 11:48:16 -04:00
|
|
|
// parse args
|
2014-10-04 09:36:39 -04:00
|
|
|
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
|
|
|
|
mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
|
2014-04-02 10:09:36 -04:00
|
|
|
|
2014-04-21 11:48:16 -04:00
|
|
|
// set the TIM configuration values
|
|
|
|
TIM_Base_InitTypeDef *init = &self->tim.Init;
|
2014-04-02 10:09:36 -04:00
|
|
|
|
2018-07-03 20:58:30 -04:00
|
|
|
if (args[ARG_freq].u_obj != mp_const_none) {
|
2014-10-04 09:36:39 -04:00
|
|
|
// set prescaler and period from desired frequency
|
2018-07-03 20:58:30 -04:00
|
|
|
init->Prescaler = compute_prescaler_period_from_freq(self, args[ARG_freq].u_obj, &init->Period);
|
|
|
|
} else if (args[ARG_prescaler].u_int != 0xffffffff && args[ARG_period].u_int != 0xffffffff) {
|
2014-04-21 11:48:16 -04:00
|
|
|
// set prescaler and period directly
|
2018-07-03 20:58:30 -04:00
|
|
|
init->Prescaler = args[ARG_prescaler].u_int;
|
|
|
|
init->Period = args[ARG_period].u_int;
|
2018-07-03 21:56:36 -04:00
|
|
|
} else if (args[ARG_period].u_int != 0xffffffff) {
|
|
|
|
// set prescaler and period from desired period and tick_hz scale
|
|
|
|
init->Prescaler = compute_prescaler_period_from_t(self, args[ARG_period].u_int, args[ARG_tick_hz].u_int, &init->Period);
|
2014-04-21 11:48:16 -04:00
|
|
|
} else {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_TypeError(MP_ERROR_TEXT("must specify either freq, period, or prescaler and period"));
|
2014-04-21 11:48:16 -04:00
|
|
|
}
|
|
|
|
|
2018-07-03 20:58:30 -04:00
|
|
|
init->CounterMode = args[ARG_mode].u_int;
|
2014-10-04 09:36:39 -04:00
|
|
|
if (!IS_TIM_COUNTER_MODE(init->CounterMode)) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid mode (%d)"), init->CounterMode);
|
2014-10-04 09:36:39 -04:00
|
|
|
}
|
2014-08-20 16:21:11 -04:00
|
|
|
|
2018-07-03 20:58:30 -04:00
|
|
|
init->ClockDivision = args[ARG_div].u_int == 2 ? TIM_CLOCKDIVISION_DIV2 :
|
|
|
|
args[ARG_div].u_int == 4 ? TIM_CLOCKDIVISION_DIV4 :
|
|
|
|
TIM_CLOCKDIVISION_DIV1;
|
2014-04-21 11:48:16 -04:00
|
|
|
|
2022-09-19 04:56:31 -04:00
|
|
|
#if !defined(STM32L0) && !defined(STM32L1)
|
2014-10-04 09:36:39 -04:00
|
|
|
init->RepetitionCounter = 0;
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2014-08-20 16:21:11 -04:00
|
|
|
|
2014-10-04 09:36:39 -04:00
|
|
|
// enable TIM clock
|
2014-04-21 11:48:16 -04:00
|
|
|
switch (self->tim_id) {
|
2019-07-05 03:24:59 -04:00
|
|
|
#if defined(TIM1)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 1:
|
|
|
|
__HAL_RCC_TIM1_CLK_ENABLE();
|
|
|
|
break;
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2018-02-12 23:37:35 -05:00
|
|
|
case 2:
|
|
|
|
__HAL_RCC_TIM2_CLK_ENABLE();
|
|
|
|
break;
|
2018-11-30 20:38:29 -05:00
|
|
|
#if defined(TIM3)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 3:
|
|
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
|
|
break;
|
2018-11-30 20:38:29 -05:00
|
|
|
#endif
|
2018-02-12 23:53:39 -05:00
|
|
|
#if defined(TIM4)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 4:
|
|
|
|
__HAL_RCC_TIM4_CLK_ENABLE();
|
|
|
|
break;
|
2018-02-12 23:53:39 -05:00
|
|
|
#endif
|
|
|
|
#if defined(TIM5)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 5:
|
|
|
|
__HAL_RCC_TIM5_CLK_ENABLE();
|
|
|
|
break;
|
2018-02-12 23:53:39 -05:00
|
|
|
#endif
|
2015-04-18 10:54:15 -04:00
|
|
|
#if defined(TIM6)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 6:
|
|
|
|
__HAL_RCC_TIM6_CLK_ENABLE();
|
|
|
|
break;
|
2015-04-18 10:54:15 -04:00
|
|
|
#endif
|
|
|
|
#if defined(TIM7)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 7:
|
|
|
|
__HAL_RCC_TIM7_CLK_ENABLE();
|
|
|
|
break;
|
2015-04-18 10:54:15 -04:00
|
|
|
#endif
|
|
|
|
#if defined(TIM8)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 8:
|
|
|
|
__HAL_RCC_TIM8_CLK_ENABLE();
|
|
|
|
break;
|
2015-04-18 10:54:15 -04:00
|
|
|
#endif
|
2016-03-22 12:07:43 -04:00
|
|
|
#if defined(TIM9)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 9:
|
|
|
|
__HAL_RCC_TIM9_CLK_ENABLE();
|
|
|
|
break;
|
2016-03-22 12:07:43 -04:00
|
|
|
#endif
|
|
|
|
#if defined(TIM10)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 10:
|
|
|
|
__HAL_RCC_TIM10_CLK_ENABLE();
|
|
|
|
break;
|
2016-03-22 12:07:43 -04:00
|
|
|
#endif
|
|
|
|
#if defined(TIM11)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 11:
|
|
|
|
__HAL_RCC_TIM11_CLK_ENABLE();
|
|
|
|
break;
|
2016-03-22 12:07:43 -04:00
|
|
|
#endif
|
2015-04-18 10:54:15 -04:00
|
|
|
#if defined(TIM12)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 12:
|
|
|
|
__HAL_RCC_TIM12_CLK_ENABLE();
|
|
|
|
break;
|
2015-04-18 10:54:15 -04:00
|
|
|
#endif
|
|
|
|
#if defined(TIM13)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 13:
|
|
|
|
__HAL_RCC_TIM13_CLK_ENABLE();
|
|
|
|
break;
|
2015-04-18 10:54:15 -04:00
|
|
|
#endif
|
|
|
|
#if defined(TIM14)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 14:
|
|
|
|
__HAL_RCC_TIM14_CLK_ENABLE();
|
|
|
|
break;
|
2015-04-18 10:54:15 -04:00
|
|
|
#endif
|
2016-03-22 12:07:43 -04:00
|
|
|
#if defined(TIM15)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 15:
|
|
|
|
__HAL_RCC_TIM15_CLK_ENABLE();
|
|
|
|
break;
|
2016-03-22 12:07:43 -04:00
|
|
|
#endif
|
|
|
|
#if defined(TIM16)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 16:
|
|
|
|
__HAL_RCC_TIM16_CLK_ENABLE();
|
|
|
|
break;
|
2016-03-22 12:07:43 -04:00
|
|
|
#endif
|
|
|
|
#if defined(TIM17)
|
2018-02-12 23:37:35 -05:00
|
|
|
case 17:
|
|
|
|
__HAL_RCC_TIM17_CLK_ENABLE();
|
|
|
|
break;
|
2016-03-22 12:07:43 -04:00
|
|
|
#endif
|
2019-07-05 03:24:59 -04:00
|
|
|
#if defined(TIM18)
|
|
|
|
case 18:
|
|
|
|
__HAL_RCC_TIM18_CLK_ENABLE();
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(TIM19)
|
|
|
|
case 19:
|
|
|
|
__HAL_RCC_TIM19_CLK_ENABLE();
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(TIM20)
|
|
|
|
case 20:
|
|
|
|
__HAL_RCC_TIM20_CLK_ENABLE();
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(TIM21)
|
|
|
|
case 21:
|
|
|
|
__HAL_RCC_TIM21_CLK_ENABLE();
|
|
|
|
break;
|
|
|
|
#endif
|
|
|
|
#if defined(TIM22)
|
|
|
|
case 22:
|
|
|
|
__HAL_RCC_TIM22_CLK_ENABLE();
|
|
|
|
break;
|
|
|
|
#endif
|
2014-04-21 11:48:16 -04:00
|
|
|
}
|
2014-10-04 09:36:39 -04:00
|
|
|
|
|
|
|
// set IRQ priority (if not a special timer)
|
2016-08-21 22:24:49 -04:00
|
|
|
if (self->tim_id != 5) {
|
2018-05-02 00:41:02 -04:00
|
|
|
NVIC_SetPriority(IRQn_NONNEG(self->irqn), IRQ_PRI_TIMX);
|
2016-08-18 23:47:49 -04:00
|
|
|
if (self->tim_id == 1) {
|
2019-07-05 03:24:59 -04:00
|
|
|
#if defined(TIM1)
|
2018-05-02 00:41:02 -04:00
|
|
|
NVIC_SetPriority(TIM1_CC_IRQn, IRQ_PRI_TIMX);
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2016-08-18 23:47:49 -04:00
|
|
|
} else if (self->tim_id == 8) {
|
2019-07-05 03:24:59 -04:00
|
|
|
#if defined(TIM8)
|
2018-05-02 00:41:02 -04:00
|
|
|
NVIC_SetPriority(TIM8_CC_IRQn, IRQ_PRI_TIMX);
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2016-08-18 23:47:49 -04:00
|
|
|
}
|
2014-04-21 11:48:16 -04:00
|
|
|
}
|
2014-04-02 10:09:36 -04:00
|
|
|
|
2014-10-04 09:36:39 -04:00
|
|
|
// init TIM
|
2014-08-20 16:21:11 -04:00
|
|
|
HAL_TIM_Base_Init(&self->tim);
|
2022-09-19 04:56:31 -04:00
|
|
|
#if !defined(STM32L0) && !defined(STM32L1)
|
2016-03-22 12:07:43 -04:00
|
|
|
#if defined(IS_TIM_ADVANCED_INSTANCE)
|
2020-06-29 02:06:30 -04:00
|
|
|
if (IS_TIM_ADVANCED_INSTANCE(self->tim.Instance))
|
2016-03-22 12:07:43 -04:00
|
|
|
#elif defined(IS_TIM_BREAK_INSTANCE)
|
2020-06-29 02:06:30 -04:00
|
|
|
if (IS_TIM_BREAK_INSTANCE(self->tim.Instance))
|
2016-03-22 12:07:43 -04:00
|
|
|
#else
|
2020-06-29 02:06:30 -04:00
|
|
|
if (0)
|
|
|
|
#endif
|
|
|
|
{
|
2019-03-14 07:15:35 -04:00
|
|
|
config_deadtime(self, args[ARG_deadtime].u_int, args[ARG_brk].u_int);
|
2014-10-10 12:56:41 -04:00
|
|
|
}
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2017-09-25 01:25:08 -04:00
|
|
|
|
|
|
|
// Enable ARPE so that the auto-reload register is buffered.
|
|
|
|
// This allows to smoothly change the frequency of the timer.
|
|
|
|
self->tim.Instance->CR1 |= TIM_CR1_ARPE;
|
|
|
|
|
|
|
|
// Start the timer running
|
2018-07-03 20:58:30 -04:00
|
|
|
if (args[ARG_callback].u_obj == mp_const_none) {
|
2014-08-20 16:21:11 -04:00
|
|
|
HAL_TIM_Base_Start(&self->tim);
|
|
|
|
} else {
|
2018-07-03 20:58:30 -04:00
|
|
|
pyb_timer_callback(MP_OBJ_FROM_PTR(self), args[ARG_callback].u_obj);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
|
2014-04-02 10:09:36 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
|
2018-06-14 20:50:08 -04:00
|
|
|
// This table encodes the timer instance and irq number (for the update irq).
|
2017-09-13 02:20:42 -04:00
|
|
|
// It assumes that timer instance pointer has the lower 8 bits cleared.
|
|
|
|
#define TIM_ENTRY(id, irq) [id - 1] = (uint32_t)TIM##id | irq
|
|
|
|
STATIC const uint32_t tim_instance_table[MICROPY_HW_MAX_TIMER] = {
|
2019-07-05 03:24:59 -04:00
|
|
|
#if defined(TIM1)
|
2022-02-12 15:36:58 -05:00
|
|
|
#if defined(STM32F0) || defined(STM32G0)
|
2018-06-14 20:50:08 -04:00
|
|
|
TIM_ENTRY(1, TIM1_BRK_UP_TRG_COM_IRQn),
|
|
|
|
#elif defined(STM32F4) || defined(STM32F7)
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(1, TIM1_UP_TIM10_IRQn),
|
2019-12-17 12:43:26 -05:00
|
|
|
#elif defined(STM32H7)
|
|
|
|
TIM_ENTRY(1, TIM1_UP_IRQn),
|
2021-01-26 08:49:56 -05:00
|
|
|
#elif defined(STM32G4) || defined(STM32L4) || defined(STM32WB)
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(1, TIM1_UP_TIM16_IRQn),
|
|
|
|
#endif
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(2, TIM2_IRQn),
|
2018-11-30 20:38:29 -05:00
|
|
|
#if defined(TIM3)
|
2022-02-12 15:36:58 -05:00
|
|
|
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
|
|
|
TIM_ENTRY(3, TIM3_TIM4_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(3, TIM3_IRQn),
|
2018-11-30 20:38:29 -05:00
|
|
|
#endif
|
2022-02-12 15:36:58 -05:00
|
|
|
#endif
|
2018-02-12 23:53:39 -05:00
|
|
|
#if defined(TIM4)
|
2022-02-12 15:36:58 -05:00
|
|
|
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
|
|
|
TIM_ENTRY(3, TIM3_TIM4_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(4, TIM4_IRQn),
|
2018-02-12 23:53:39 -05:00
|
|
|
#endif
|
2022-02-12 15:36:58 -05:00
|
|
|
#endif
|
2018-02-12 23:53:39 -05:00
|
|
|
#if defined(TIM5)
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(5, TIM5_IRQn),
|
2018-02-12 23:53:39 -05:00
|
|
|
#endif
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM6)
|
2022-09-19 04:56:31 -04:00
|
|
|
#if defined(STM32F412Zx) || defined(STM32L1)
|
2020-05-14 09:56:26 -04:00
|
|
|
TIM_ENTRY(6, TIM6_IRQn),
|
2022-02-12 15:36:58 -05:00
|
|
|
#elif defined(STM32G0)
|
|
|
|
TIM_ENTRY(6, TIM6_DAC_LPTIM1_IRQn),
|
2023-03-22 01:38:49 -04:00
|
|
|
#elif defined(STM32H5)
|
|
|
|
TIM_ENTRY(6, TIM6_IRQn),
|
2020-05-14 09:56:26 -04:00
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(6, TIM6_DAC_IRQn),
|
|
|
|
#endif
|
2020-05-14 09:56:26 -04:00
|
|
|
#endif
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM7)
|
2022-02-12 15:36:58 -05:00
|
|
|
#if defined(STM32G0)
|
|
|
|
TIM_ENTRY(7, TIM7_LPTIM2_IRQn),
|
|
|
|
#elif defined(STM32G4)
|
2021-01-26 08:49:56 -05:00
|
|
|
TIM_ENTRY(7, TIM7_DAC_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(7, TIM7_IRQn),
|
|
|
|
#endif
|
2021-01-26 08:49:56 -05:00
|
|
|
#endif
|
2023-09-13 02:07:49 -04:00
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM8)
|
2019-12-17 12:43:26 -05:00
|
|
|
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(8, TIM8_UP_TIM13_IRQn),
|
2023-09-13 02:07:49 -04:00
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(8, TIM8_UP_IRQn),
|
|
|
|
#endif
|
|
|
|
#endif
|
2023-03-22 01:38:49 -04:00
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM9)
|
2022-09-19 04:56:31 -04:00
|
|
|
#if defined(STM32L1)
|
|
|
|
TIM_ENTRY(9, TIM9_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(9, TIM1_BRK_TIM9_IRQn),
|
|
|
|
#endif
|
2022-09-19 04:56:31 -04:00
|
|
|
#endif
|
2023-03-22 01:38:49 -04:00
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM10)
|
2022-09-19 04:56:31 -04:00
|
|
|
#if defined(STM32L1)
|
|
|
|
TIM_ENTRY(10, TIM10_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(10, TIM1_UP_TIM10_IRQn),
|
|
|
|
#endif
|
2022-09-19 04:56:31 -04:00
|
|
|
#endif
|
2023-03-22 01:38:49 -04:00
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM11)
|
2022-09-19 04:56:31 -04:00
|
|
|
#if defined(STM32L1)
|
|
|
|
TIM_ENTRY(11, TIM11_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(11, TIM1_TRG_COM_TIM11_IRQn),
|
|
|
|
#endif
|
2022-09-19 04:56:31 -04:00
|
|
|
#endif
|
2023-03-22 01:38:49 -04:00
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM12)
|
2023-03-22 01:38:49 -04:00
|
|
|
#if defined(STM32H5)
|
|
|
|
TIM_ENTRY(12, TIM12_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(12, TIM8_BRK_TIM12_IRQn),
|
|
|
|
#endif
|
2023-03-22 01:38:49 -04:00
|
|
|
#endif
|
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM13)
|
2023-03-22 01:38:49 -04:00
|
|
|
#if defined(STM32H5)
|
|
|
|
TIM_ENTRY(13, TIM13_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(13, TIM8_UP_TIM13_IRQn),
|
|
|
|
#endif
|
2023-03-22 01:38:49 -04:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#if defined(STM32F0) || defined(STM32G0) || defined(STM32H5)
|
2018-05-28 04:10:53 -04:00
|
|
|
TIM_ENTRY(14, TIM14_IRQn),
|
|
|
|
#elif defined(TIM14)
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(14, TIM8_TRG_COM_TIM14_IRQn),
|
|
|
|
#endif
|
2023-03-22 01:38:49 -04:00
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM15)
|
2023-03-22 01:38:49 -04:00
|
|
|
#if defined(STM32F0) || defined(STM32G0) || defined(STM32H5) || defined(STM32H7)
|
2018-02-23 11:53:29 -05:00
|
|
|
TIM_ENTRY(15, TIM15_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(15, TIM1_BRK_TIM15_IRQn),
|
|
|
|
#endif
|
2018-02-23 11:53:29 -05:00
|
|
|
#endif
|
2023-03-22 01:38:49 -04:00
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM16)
|
2022-02-12 15:36:58 -05:00
|
|
|
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
|
|
|
TIM_ENTRY(16, TIM16_FDCAN_IT0_IRQn),
|
2023-03-22 01:38:49 -04:00
|
|
|
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32H5) || defined(STM32H7) || defined(STM32WL)
|
2018-02-23 11:53:29 -05:00
|
|
|
TIM_ENTRY(16, TIM16_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(16, TIM1_UP_TIM16_IRQn),
|
|
|
|
#endif
|
2018-02-23 11:53:29 -05:00
|
|
|
#endif
|
2023-03-22 01:38:49 -04:00
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
#if defined(TIM17)
|
2022-02-12 15:36:58 -05:00
|
|
|
#if defined(STM32G0B1xx) || defined(STM32G0C1xx)
|
|
|
|
TIM_ENTRY(17, TIM17_FDCAN_IT1_IRQn),
|
2023-03-22 01:38:49 -04:00
|
|
|
#elif defined(STM32F0) || defined(STM32G0) || defined(STM32H5) || defined(STM32H7) || defined(STM32WL)
|
2018-02-23 11:53:29 -05:00
|
|
|
TIM_ENTRY(17, TIM17_IRQn),
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
TIM_ENTRY(17, TIM1_TRG_COM_TIM17_IRQn),
|
|
|
|
#endif
|
2018-02-23 11:53:29 -05:00
|
|
|
#endif
|
2023-03-22 01:38:49 -04:00
|
|
|
|
2021-01-26 08:49:56 -05:00
|
|
|
#if defined(TIM20)
|
|
|
|
TIM_ENTRY(20, TIM20_UP_IRQn),
|
|
|
|
#endif
|
2017-09-13 02:20:42 -04:00
|
|
|
};
|
|
|
|
#undef TIM_ENTRY
|
|
|
|
|
2014-05-02 11:58:15 -04:00
|
|
|
/// \classmethod \constructor(id, ...)
|
|
|
|
/// Construct a new timer object of the given id. If additional
|
|
|
|
/// arguments are given, then the timer is initialised by `init(...)`.
|
|
|
|
/// `id` can be 1 to 14, excluding 3.
|
2017-01-04 08:10:42 -05:00
|
|
|
STATIC mp_obj_t pyb_timer_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
|
2014-04-21 11:48:16 -04:00
|
|
|
// check arguments
|
|
|
|
mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true);
|
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
// get the timer id
|
|
|
|
mp_int_t tim_id = mp_obj_get_int(args[0]);
|
2014-04-21 11:48:16 -04:00
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
// check if the timer exists
|
|
|
|
if (tim_id <= 0 || tim_id > MICROPY_HW_MAX_TIMER || tim_instance_table[tim_id - 1] == 0) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Timer(%d) doesn't exist"), tim_id);
|
2014-04-21 11:48:16 -04:00
|
|
|
}
|
|
|
|
|
2020-12-02 21:07:37 -05:00
|
|
|
// check if the timer is reserved for system use or not
|
|
|
|
if (MICROPY_HW_TIM_IS_RESERVED(tim_id)) {
|
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Timer(%d) is reserved"), tim_id);
|
|
|
|
}
|
|
|
|
|
2017-09-13 02:20:42 -04:00
|
|
|
pyb_timer_obj_t *tim;
|
|
|
|
if (MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1] == NULL) {
|
|
|
|
// create new Timer object
|
|
|
|
tim = m_new_obj(pyb_timer_obj_t);
|
|
|
|
memset(tim, 0, sizeof(*tim));
|
|
|
|
tim->base.type = &pyb_timer_type;
|
|
|
|
tim->tim_id = tim_id;
|
2022-09-19 04:56:31 -04:00
|
|
|
#if defined(STM32L1)
|
|
|
|
tim->is_32bit = tim_id == 5;
|
|
|
|
#else
|
2017-09-13 02:20:42 -04:00
|
|
|
tim->is_32bit = tim_id == 2 || tim_id == 5;
|
2022-09-19 04:56:31 -04:00
|
|
|
#endif
|
2017-09-13 02:20:42 -04:00
|
|
|
tim->callback = mp_const_none;
|
|
|
|
uint32_t ti = tim_instance_table[tim_id - 1];
|
|
|
|
tim->tim.Instance = (TIM_TypeDef *)(ti & 0xffffff00);
|
|
|
|
tim->irqn = ti & 0xff;
|
|
|
|
MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1] = tim;
|
|
|
|
} else {
|
|
|
|
// reference existing Timer object
|
|
|
|
tim = MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1];
|
2015-02-22 22:58:51 -05:00
|
|
|
}
|
|
|
|
|
2014-04-21 11:48:16 -04:00
|
|
|
if (n_args > 1 || n_kw > 0) {
|
|
|
|
// start the peripheral
|
|
|
|
mp_map_t kw_args;
|
|
|
|
mp_map_init_fixed_table(&kw_args, n_kw, args + n_args);
|
|
|
|
pyb_timer_init_helper(tim, n_args - 1, args + 1, &kw_args);
|
|
|
|
}
|
|
|
|
|
2018-07-08 09:25:11 -04:00
|
|
|
return MP_OBJ_FROM_PTR(tim);
|
2014-04-02 10:09:36 -04:00
|
|
|
}
|
|
|
|
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) {
|
2018-07-08 09:25:11 -04:00
|
|
|
return pyb_timer_init_helper(MP_OBJ_TO_PTR(args[0]), n_args - 1, args + 1, kw_args);
|
2014-04-02 10:09:36 -04:00
|
|
|
}
|
2014-04-21 11:48:16 -04:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_timer_init_obj, 1, pyb_timer_init);
|
2014-04-02 10:09:36 -04:00
|
|
|
|
2015-02-13 06:57:29 -05:00
|
|
|
// timer.deinit()
|
2014-04-21 11:48:16 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_deinit(mp_obj_t self_in) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
2014-06-30 10:55:54 -04:00
|
|
|
|
2014-08-20 16:21:11 -04:00
|
|
|
// Disable the base interrupt
|
2014-06-30 10:55:54 -04:00
|
|
|
pyb_timer_callback(self_in, mp_const_none);
|
|
|
|
|
2014-08-20 16:21:11 -04:00
|
|
|
pyb_timer_channel_obj_t *chan = self->channel;
|
|
|
|
self->channel = NULL;
|
|
|
|
|
|
|
|
// Disable the channel interrupts
|
|
|
|
while (chan != NULL) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_channel_callback(MP_OBJ_FROM_PTR(chan), mp_const_none);
|
2014-08-20 16:21:11 -04:00
|
|
|
pyb_timer_channel_obj_t *prev_chan = chan;
|
|
|
|
chan = chan->next;
|
|
|
|
prev_chan->next = NULL;
|
|
|
|
}
|
|
|
|
|
2015-02-23 08:18:14 -05:00
|
|
|
self->tim.State = HAL_TIM_STATE_RESET;
|
2015-02-13 06:57:29 -05:00
|
|
|
self->tim.Instance->CCER = 0x0000; // disable all capture/compare outputs
|
|
|
|
self->tim.Instance->CR1 = 0x0000; // disable the timer and reset its state
|
|
|
|
|
2014-04-21 11:48:16 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_timer_deinit_obj, pyb_timer_deinit);
|
|
|
|
|
2014-08-20 16:21:11 -04:00
|
|
|
/// \method channel(channel, mode, ...)
|
|
|
|
///
|
2014-09-21 17:54:02 -04:00
|
|
|
/// If only a channel number is passed, then a previously initialized channel
|
|
|
|
/// object is returned (or `None` if there is no previous channel).
|
2014-08-20 16:21:11 -04:00
|
|
|
///
|
|
|
|
/// Otherwise, a TimerChannel object is initialized and returned.
|
|
|
|
///
|
|
|
|
/// Each channel can be configured to perform pwm, output compare, or
|
|
|
|
/// input capture. All channels share the same underlying timer, which means
|
|
|
|
/// that they share the same timer clock.
|
|
|
|
///
|
|
|
|
/// Keyword arguments:
|
|
|
|
///
|
|
|
|
/// - `mode` can be one of:
|
|
|
|
/// - `Timer.PWM` - configure the timer in PWM mode (active high).
|
|
|
|
/// - `Timer.PWM_INVERTED` - configure the timer in PWM mode (active low).
|
|
|
|
/// - `Timer.OC_TIMING` - indicates that no pin is driven.
|
|
|
|
/// - `Timer.OC_ACTIVE` - the pin will be made active when a compare
|
|
|
|
/// match occurs (active is determined by polarity)
|
|
|
|
/// - `Timer.OC_INACTIVE` - the pin will be made inactive when a compare
|
|
|
|
/// match occurs.
|
|
|
|
/// - `Timer.OC_TOGGLE` - the pin will be toggled when an compare match occurs.
|
|
|
|
/// - `Timer.OC_FORCED_ACTIVE` - the pin is forced active (compare match is ignored).
|
|
|
|
/// - `Timer.OC_FORCED_INACTIVE` - the pin is forced inactive (compare match is ignored).
|
|
|
|
/// - `Timer.IC` - configure the timer in Input Capture mode.
|
2015-03-09 04:04:12 -04:00
|
|
|
/// - `Timer.ENC_A` --- configure the timer in Encoder mode. The counter only changes when CH1 changes.
|
|
|
|
/// - `Timer.ENC_B` --- configure the timer in Encoder mode. The counter only changes when CH2 changes.
|
|
|
|
/// - `Timer.ENC_AB` --- configure the timer in Encoder mode. The counter changes when CH1 or CH2 changes.
|
2014-08-20 16:21:11 -04:00
|
|
|
///
|
|
|
|
/// - `callback` - as per TimerChannel.callback()
|
|
|
|
///
|
|
|
|
/// - `pin` None (the default) or a Pin object. If specified (and not None)
|
|
|
|
/// this will cause the alternate function of the the indicated pin
|
|
|
|
/// to be configured for this timer channel. An error will be raised if
|
|
|
|
/// the pin doesn't support any alternate functions for this timer channel.
|
|
|
|
///
|
|
|
|
/// Keyword arguments for Timer.PWM modes:
|
|
|
|
///
|
2014-09-21 17:54:02 -04:00
|
|
|
/// - `pulse_width` - determines the initial pulse width value to use.
|
2014-09-22 01:40:42 -04:00
|
|
|
/// - `pulse_width_percent` - determines the initial pulse width percentage to use.
|
2014-08-20 16:21:11 -04:00
|
|
|
///
|
|
|
|
/// Keyword arguments for Timer.OC modes:
|
|
|
|
///
|
|
|
|
/// - `compare` - determines the initial value of the compare register.
|
|
|
|
///
|
|
|
|
/// - `polarity` can be one of:
|
|
|
|
/// - `Timer.HIGH` - output is active high
|
|
|
|
/// - `Timer.LOW` - output is active low
|
|
|
|
///
|
|
|
|
/// Optional keyword arguments for Timer.IC modes:
|
|
|
|
///
|
|
|
|
/// - `polarity` can be one of:
|
|
|
|
/// - `Timer.RISING` - captures on rising edge.
|
|
|
|
/// - `Timer.FALLING` - captures on falling edge.
|
|
|
|
/// - `Timer.BOTH` - captures on both edges.
|
|
|
|
///
|
2014-10-10 12:56:41 -04:00
|
|
|
/// Note that capture only works on the primary channel, and not on the
|
|
|
|
/// complimentary channels.
|
|
|
|
///
|
2015-03-09 04:04:12 -04:00
|
|
|
/// Notes for Timer.ENC modes:
|
|
|
|
///
|
|
|
|
/// - Requires 2 pins, so one or both pins will need to be configured to use
|
|
|
|
/// the appropriate timer AF using the Pin API.
|
|
|
|
/// - Read the encoder value using the timer.counter() method.
|
|
|
|
/// - Only works on CH1 and CH2 (and not on CH1N or CH2N)
|
|
|
|
/// - The channel number is ignored when setting the encoder mode.
|
|
|
|
///
|
2014-08-20 16:21:11 -04:00
|
|
|
/// PWM Example:
|
|
|
|
///
|
|
|
|
/// timer = pyb.Timer(2, freq=1000)
|
|
|
|
/// ch2 = timer.channel(2, pyb.Timer.PWM, pin=pyb.Pin.board.X2, pulse_width=210000)
|
|
|
|
/// ch3 = timer.channel(3, pyb.Timer.PWM, pin=pyb.Pin.board.X3, pulse_width=420000)
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_channel(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) {
|
2014-10-04 10:25:01 -04:00
|
|
|
static const mp_arg_t allowed_args[] = {
|
|
|
|
{ MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} },
|
2019-12-15 23:40:05 -05:00
|
|
|
{ MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
|
|
|
|
{ MP_QSTR_pin, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
|
2014-10-04 10:25:01 -04:00
|
|
|
{ MP_QSTR_pulse_width, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
|
2019-12-15 23:40:05 -05:00
|
|
|
{ MP_QSTR_pulse_width_percent, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} },
|
2014-10-04 10:25:01 -04:00
|
|
|
{ MP_QSTR_compare, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
|
|
|
|
{ MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0xffffffff} },
|
|
|
|
};
|
2014-08-20 16:21:11 -04:00
|
|
|
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]);
|
2014-10-04 10:25:01 -04:00
|
|
|
mp_int_t channel = mp_obj_get_int(pos_args[1]);
|
2014-08-20 16:21:11 -04:00
|
|
|
|
|
|
|
if (channel < 1 || channel > 4) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid channel (%d)"), channel);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
pyb_timer_channel_obj_t *chan = self->channel;
|
|
|
|
pyb_timer_channel_obj_t *prev_chan = NULL;
|
|
|
|
|
|
|
|
while (chan != NULL) {
|
|
|
|
if (chan->channel == channel) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
prev_chan = chan;
|
|
|
|
chan = chan->next;
|
|
|
|
}
|
2014-09-21 17:54:02 -04:00
|
|
|
|
|
|
|
// If only the channel number is given return the previously allocated
|
|
|
|
// channel (or None if no previous channel).
|
2014-10-04 10:25:01 -04:00
|
|
|
if (n_args == 2 && kw_args->used == 0) {
|
2014-08-20 16:21:11 -04:00
|
|
|
if (chan) {
|
2018-07-08 09:25:11 -04:00
|
|
|
return MP_OBJ_FROM_PTR(chan);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
|
|
|
|
// If there was already a channel, then remove it from the list. Note that
|
|
|
|
// the order we do things here is important so as to appear atomic to
|
|
|
|
// the IRQ handler.
|
|
|
|
if (chan) {
|
|
|
|
// Turn off any IRQ associated with the channel.
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_channel_callback(MP_OBJ_FROM_PTR(chan), mp_const_none);
|
2014-08-20 16:21:11 -04:00
|
|
|
|
|
|
|
// Unlink the channel from the list.
|
|
|
|
if (prev_chan) {
|
|
|
|
prev_chan->next = chan->next;
|
|
|
|
}
|
|
|
|
self->channel = chan->next;
|
|
|
|
chan->next = NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Allocate and initialize a new channel
|
2014-10-04 10:25:01 -04:00
|
|
|
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
|
|
|
|
mp_arg_parse_all(n_args - 2, pos_args + 2, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
|
2014-08-20 16:21:11 -04:00
|
|
|
|
|
|
|
chan = m_new_obj(pyb_timer_channel_obj_t);
|
|
|
|
memset(chan, 0, sizeof(*chan));
|
|
|
|
chan->base.type = &pyb_timer_channel_type;
|
|
|
|
chan->timer = self;
|
|
|
|
chan->channel = channel;
|
2014-10-04 10:25:01 -04:00
|
|
|
chan->mode = args[0].u_int;
|
|
|
|
chan->callback = args[1].u_obj;
|
2014-08-20 16:21:11 -04:00
|
|
|
|
2014-10-04 10:25:01 -04:00
|
|
|
mp_obj_t pin_obj = args[2].u_obj;
|
2014-08-20 16:21:11 -04:00
|
|
|
if (pin_obj != mp_const_none) {
|
2019-01-30 06:05:48 -05:00
|
|
|
if (!mp_obj_is_type(pin_obj, &pin_type)) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("pin argument needs to be be a Pin type"));
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
2018-07-08 09:25:11 -04:00
|
|
|
const pin_obj_t *pin = MP_OBJ_TO_PTR(pin_obj);
|
2014-08-20 16:21:11 -04:00
|
|
|
const pin_af_obj_t *af = pin_find_af(pin, AF_FN_TIM, self->tim_id);
|
|
|
|
if (af == NULL) {
|
2022-01-27 00:36:08 -05:00
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Pin(%q) doesn't have an alt for Timer(%d)"), pin->name, self->tim_id);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
2022-01-27 00:36:08 -05:00
|
|
|
// pin.init(mode=AF_PP, alt=idx)
|
2014-10-04 10:25:01 -04:00
|
|
|
const mp_obj_t args2[6] = {
|
2018-07-08 09:25:11 -04:00
|
|
|
MP_OBJ_FROM_PTR(&pin_init_obj),
|
2014-08-20 16:21:11 -04:00
|
|
|
pin_obj,
|
|
|
|
MP_OBJ_NEW_QSTR(MP_QSTR_mode), MP_OBJ_NEW_SMALL_INT(GPIO_MODE_AF_PP),
|
2022-01-27 00:36:08 -05:00
|
|
|
MP_OBJ_NEW_QSTR(MP_QSTR_alt), MP_OBJ_NEW_SMALL_INT(af->idx)
|
2014-08-20 16:21:11 -04:00
|
|
|
};
|
2014-10-04 10:25:01 -04:00
|
|
|
mp_call_method_n_kw(0, 2, args2);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
// Link the channel to the timer before we turn the channel on.
|
|
|
|
// Note that this needs to appear atomic to the IRQ handler (the write
|
|
|
|
// to self->channel is atomic, so we're good, but I thought I'd mention
|
|
|
|
// in case this was ever changed in the future).
|
|
|
|
chan->next = self->channel;
|
|
|
|
self->channel = chan;
|
|
|
|
|
|
|
|
switch (chan->mode) {
|
|
|
|
|
|
|
|
case CHANNEL_MODE_PWM_NORMAL:
|
|
|
|
case CHANNEL_MODE_PWM_INVERTED: {
|
|
|
|
TIM_OC_InitTypeDef oc_config;
|
2014-09-21 17:54:02 -04:00
|
|
|
oc_config.OCMode = channel_mode_info[chan->mode].oc_mode;
|
2014-10-04 10:25:01 -04:00
|
|
|
if (args[4].u_obj != mp_const_none) {
|
2014-09-22 01:40:42 -04:00
|
|
|
// pulse width percent given
|
2014-09-26 12:04:05 -04:00
|
|
|
uint32_t period = compute_period(self);
|
2014-10-04 10:25:01 -04:00
|
|
|
oc_config.Pulse = compute_pwm_value_from_percent(period, args[4].u_obj);
|
2014-09-21 17:54:02 -04:00
|
|
|
} else {
|
2014-09-25 10:44:10 -04:00
|
|
|
// use absolute pulse width value (defaults to 0 if nothing given)
|
2014-10-04 10:25:01 -04:00
|
|
|
oc_config.Pulse = args[3].u_int;
|
2014-09-21 17:54:02 -04:00
|
|
|
}
|
2014-08-20 16:21:11 -04:00
|
|
|
oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
|
|
oc_config.OCFastMode = TIM_OCFAST_DISABLE;
|
2022-09-19 04:56:31 -04:00
|
|
|
#if !defined(STM32L0) && !defined(STM32L1)
|
2019-07-05 03:24:59 -04:00
|
|
|
oc_config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
|
2014-08-20 16:21:11 -04:00
|
|
|
oc_config.OCIdleState = TIM_OCIDLESTATE_SET;
|
|
|
|
oc_config.OCNIdleState = TIM_OCNIDLESTATE_SET;
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2014-08-20 16:21:11 -04:00
|
|
|
|
|
|
|
HAL_TIM_PWM_ConfigChannel(&self->tim, &oc_config, TIMER_CHANNEL(chan));
|
|
|
|
if (chan->callback == mp_const_none) {
|
|
|
|
HAL_TIM_PWM_Start(&self->tim, TIMER_CHANNEL(chan));
|
|
|
|
} else {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_channel_callback(MP_OBJ_FROM_PTR(chan), chan->callback);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
2022-09-19 04:56:31 -04:00
|
|
|
#if !defined(STM32L0) && !defined(STM32L1)
|
2014-10-10 12:56:41 -04:00
|
|
|
// Start the complimentary channel too (if its supported)
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(self->tim.Instance, TIMER_CHANNEL(chan))) {
|
|
|
|
HAL_TIMEx_PWMN_Start(&self->tim, TIMER_CHANNEL(chan));
|
|
|
|
}
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2014-08-20 16:21:11 -04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case CHANNEL_MODE_OC_TIMING:
|
|
|
|
case CHANNEL_MODE_OC_ACTIVE:
|
|
|
|
case CHANNEL_MODE_OC_INACTIVE:
|
|
|
|
case CHANNEL_MODE_OC_TOGGLE:
|
|
|
|
case CHANNEL_MODE_OC_FORCED_ACTIVE:
|
|
|
|
case CHANNEL_MODE_OC_FORCED_INACTIVE: {
|
|
|
|
TIM_OC_InitTypeDef oc_config;
|
2014-09-21 17:54:02 -04:00
|
|
|
oc_config.OCMode = channel_mode_info[chan->mode].oc_mode;
|
2014-10-04 10:25:01 -04:00
|
|
|
oc_config.Pulse = args[5].u_int;
|
|
|
|
oc_config.OCPolarity = args[6].u_int;
|
2014-08-20 16:21:11 -04:00
|
|
|
if (oc_config.OCPolarity == 0xffffffff) {
|
|
|
|
oc_config.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
|
|
}
|
2019-07-05 03:24:59 -04:00
|
|
|
oc_config.OCFastMode = TIM_OCFAST_DISABLE;
|
2022-09-19 04:56:31 -04:00
|
|
|
#if !defined(STM32L0) && !defined(STM32L1)
|
2014-10-10 12:56:41 -04:00
|
|
|
if (oc_config.OCPolarity == TIM_OCPOLARITY_HIGH) {
|
|
|
|
oc_config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
|
|
|
|
} else {
|
|
|
|
oc_config.OCNPolarity = TIM_OCNPOLARITY_LOW;
|
|
|
|
}
|
2014-08-20 16:21:11 -04:00
|
|
|
oc_config.OCIdleState = TIM_OCIDLESTATE_SET;
|
|
|
|
oc_config.OCNIdleState = TIM_OCNIDLESTATE_SET;
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2014-08-20 16:21:11 -04:00
|
|
|
|
|
|
|
if (!IS_TIM_OC_POLARITY(oc_config.OCPolarity)) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid polarity (%d)"), oc_config.OCPolarity);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
HAL_TIM_OC_ConfigChannel(&self->tim, &oc_config, TIMER_CHANNEL(chan));
|
|
|
|
if (chan->callback == mp_const_none) {
|
|
|
|
HAL_TIM_OC_Start(&self->tim, TIMER_CHANNEL(chan));
|
|
|
|
} else {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_channel_callback(MP_OBJ_FROM_PTR(chan), chan->callback);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
2022-09-19 04:56:31 -04:00
|
|
|
#if !defined(STM32L0) && !defined(STM32L1)
|
2014-10-10 12:56:41 -04:00
|
|
|
// Start the complimentary channel too (if its supported)
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(self->tim.Instance, TIMER_CHANNEL(chan))) {
|
|
|
|
HAL_TIMEx_OCN_Start(&self->tim, TIMER_CHANNEL(chan));
|
|
|
|
}
|
2019-07-05 03:24:59 -04:00
|
|
|
#endif
|
2014-08-20 16:21:11 -04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
case CHANNEL_MODE_IC: {
|
|
|
|
TIM_IC_InitTypeDef ic_config;
|
|
|
|
|
2014-10-04 10:25:01 -04:00
|
|
|
ic_config.ICPolarity = args[6].u_int;
|
2014-08-20 16:21:11 -04:00
|
|
|
if (ic_config.ICPolarity == 0xffffffff) {
|
|
|
|
ic_config.ICPolarity = TIM_ICPOLARITY_RISING;
|
|
|
|
}
|
|
|
|
ic_config.ICSelection = TIM_ICSELECTION_DIRECTTI;
|
|
|
|
ic_config.ICPrescaler = TIM_ICPSC_DIV1;
|
|
|
|
ic_config.ICFilter = 0;
|
|
|
|
|
|
|
|
if (!IS_TIM_IC_POLARITY(ic_config.ICPolarity)) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid polarity (%d)"), ic_config.ICPolarity);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
HAL_TIM_IC_ConfigChannel(&self->tim, &ic_config, TIMER_CHANNEL(chan));
|
|
|
|
if (chan->callback == mp_const_none) {
|
|
|
|
HAL_TIM_IC_Start(&self->tim, TIMER_CHANNEL(chan));
|
|
|
|
} else {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_channel_callback(MP_OBJ_FROM_PTR(chan), chan->callback);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2015-03-09 04:04:12 -04:00
|
|
|
case CHANNEL_MODE_ENC_A:
|
|
|
|
case CHANNEL_MODE_ENC_B:
|
|
|
|
case CHANNEL_MODE_ENC_AB: {
|
|
|
|
TIM_Encoder_InitTypeDef enc_config;
|
|
|
|
|
|
|
|
enc_config.EncoderMode = channel_mode_info[chan->mode].oc_mode;
|
|
|
|
enc_config.IC1Polarity = args[6].u_int;
|
|
|
|
if (enc_config.IC1Polarity == 0xffffffff) {
|
|
|
|
enc_config.IC1Polarity = TIM_ICPOLARITY_RISING;
|
|
|
|
}
|
|
|
|
enc_config.IC2Polarity = enc_config.IC1Polarity;
|
|
|
|
enc_config.IC1Selection = TIM_ICSELECTION_DIRECTTI;
|
|
|
|
enc_config.IC2Selection = TIM_ICSELECTION_DIRECTTI;
|
|
|
|
enc_config.IC1Prescaler = TIM_ICPSC_DIV1;
|
|
|
|
enc_config.IC2Prescaler = TIM_ICPSC_DIV1;
|
|
|
|
enc_config.IC1Filter = 0;
|
|
|
|
enc_config.IC2Filter = 0;
|
|
|
|
|
|
|
|
if (!IS_TIM_IC_POLARITY(enc_config.IC1Polarity)) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid polarity (%d)"), enc_config.IC1Polarity);
|
2015-03-09 04:04:12 -04:00
|
|
|
}
|
|
|
|
// Only Timers 1, 2, 3, 4, 5, and 8 support encoder mode
|
2019-07-05 03:24:59 -04:00
|
|
|
if (
|
|
|
|
#if defined(TIM1)
|
|
|
|
self->tim.Instance != TIM1
|
|
|
|
&&
|
|
|
|
#endif
|
|
|
|
self->tim.Instance != TIM2
|
2018-11-30 20:38:29 -05:00
|
|
|
#if defined(TIM3)
|
2015-03-09 04:04:12 -04:00
|
|
|
&& self->tim.Instance != TIM3
|
2018-11-30 20:38:29 -05:00
|
|
|
#endif
|
2018-02-12 23:53:39 -05:00
|
|
|
#if defined(TIM4)
|
2015-03-09 04:04:12 -04:00
|
|
|
&& self->tim.Instance != TIM4
|
2018-02-12 23:53:39 -05:00
|
|
|
#endif
|
|
|
|
#if defined(TIM5)
|
2015-03-09 04:04:12 -04:00
|
|
|
&& self->tim.Instance != TIM5
|
2018-02-12 23:53:39 -05:00
|
|
|
#endif
|
2015-04-18 10:54:15 -04:00
|
|
|
#if defined(TIM8)
|
|
|
|
&& self->tim.Instance != TIM8
|
|
|
|
#endif
|
|
|
|
) {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("encoder not supported on timer %d"), self->tim_id);
|
2015-03-09 04:04:12 -04:00
|
|
|
}
|
2015-03-10 02:44:26 -04:00
|
|
|
|
|
|
|
// Disable & clear the timer interrupt so that we don't trigger
|
|
|
|
// an interrupt by initializing the timer.
|
|
|
|
__HAL_TIM_DISABLE_IT(&self->tim, TIM_IT_UPDATE);
|
2015-03-09 04:04:12 -04:00
|
|
|
HAL_TIM_Encoder_Init(&self->tim, &enc_config);
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_TIM_SET_COUNTER(&self->tim, 0);
|
2015-03-10 02:44:26 -04:00
|
|
|
if (self->callback != mp_const_none) {
|
|
|
|
__HAL_TIM_CLEAR_FLAG(&self->tim, TIM_IT_UPDATE);
|
|
|
|
__HAL_TIM_ENABLE_IT(&self->tim, TIM_IT_UPDATE);
|
|
|
|
}
|
|
|
|
HAL_TIM_Encoder_Start(&self->tim, TIM_CHANNEL_ALL);
|
2015-03-09 04:04:12 -04:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-08-20 16:21:11 -04:00
|
|
|
default:
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid mode (%d)"), chan->mode);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
|
2018-07-08 09:25:11 -04:00
|
|
|
return MP_OBJ_FROM_PTR(chan);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
2014-09-21 17:54:02 -04:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_timer_channel_obj, 2, pyb_timer_channel);
|
2014-08-20 16:21:11 -04:00
|
|
|
|
2014-05-02 11:58:15 -04:00
|
|
|
/// \method counter([value])
|
|
|
|
/// Get or set the timer counter.
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_counter(size_t n_args, const mp_obj_t *args) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_obj_t *self = MP_OBJ_TO_PTR(args[0]);
|
2014-04-21 11:48:16 -04:00
|
|
|
if (n_args == 1) {
|
|
|
|
// get
|
|
|
|
return mp_obj_new_int(self->tim.Instance->CNT);
|
|
|
|
} else {
|
|
|
|
// set
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_TIM_SET_COUNTER(&self->tim, mp_obj_get_int(args[1]));
|
2014-04-21 11:48:16 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_counter_obj, 1, 2, pyb_timer_counter);
|
|
|
|
|
2014-10-04 09:36:39 -04:00
|
|
|
/// \method source_freq()
|
|
|
|
/// Get the frequency of the source of the timer.
|
|
|
|
STATIC mp_obj_t pyb_timer_source_freq(mp_obj_t self_in) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
2014-10-04 09:36:39 -04:00
|
|
|
uint32_t source_freq = timer_get_source_freq(self->tim_id);
|
|
|
|
return mp_obj_new_int(source_freq);
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_timer_source_freq_obj, pyb_timer_source_freq);
|
|
|
|
|
|
|
|
/// \method freq([value])
|
|
|
|
/// Get or set the frequency for the timer (changes prescaler and period if set).
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_freq(size_t n_args, const mp_obj_t *args) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_obj_t *self = MP_OBJ_TO_PTR(args[0]);
|
2014-10-04 09:36:39 -04:00
|
|
|
if (n_args == 1) {
|
|
|
|
// get
|
|
|
|
uint32_t prescaler = self->tim.Instance->PSC & 0xffff;
|
2018-02-12 23:37:35 -05:00
|
|
|
uint32_t period = __HAL_TIM_GET_AUTORELOAD(&self->tim) & TIMER_CNT_MASK(self);
|
2014-10-04 09:36:39 -04:00
|
|
|
uint32_t source_freq = timer_get_source_freq(self->tim_id);
|
2019-10-30 21:49:18 -04:00
|
|
|
uint32_t divide_a = prescaler + 1;
|
|
|
|
uint32_t divide_b = period + 1;
|
2015-01-08 12:55:55 -05:00
|
|
|
#if MICROPY_PY_BUILTINS_FLOAT
|
2019-10-30 21:49:18 -04:00
|
|
|
if (source_freq % divide_a != 0) {
|
|
|
|
return mp_obj_new_float((mp_float_t)source_freq / (mp_float_t)divide_a / (mp_float_t)divide_b);
|
|
|
|
}
|
|
|
|
source_freq /= divide_a;
|
|
|
|
if (source_freq % divide_b != 0) {
|
|
|
|
return mp_obj_new_float((mp_float_t)source_freq / (mp_float_t)divide_b);
|
|
|
|
} else {
|
|
|
|
return mp_obj_new_int(source_freq / divide_b);
|
2014-10-04 09:36:39 -04:00
|
|
|
}
|
2019-10-30 21:49:18 -04:00
|
|
|
#else
|
|
|
|
return mp_obj_new_int(source_freq / divide_a / divide_b);
|
|
|
|
#endif
|
2014-10-04 09:36:39 -04:00
|
|
|
} else {
|
|
|
|
// set
|
|
|
|
uint32_t period;
|
|
|
|
uint32_t prescaler = compute_prescaler_period_from_freq(self, args[1], &period);
|
|
|
|
self->tim.Instance->PSC = prescaler;
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_TIM_SET_AUTORELOAD(&self->tim, period);
|
2014-10-04 09:36:39 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_freq_obj, 1, 2, pyb_timer_freq);
|
|
|
|
|
2014-05-02 11:58:15 -04:00
|
|
|
/// \method prescaler([value])
|
|
|
|
/// Get or set the prescaler for the timer.
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_prescaler(size_t n_args, const mp_obj_t *args) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_obj_t *self = MP_OBJ_TO_PTR(args[0]);
|
2014-04-21 11:48:16 -04:00
|
|
|
if (n_args == 1) {
|
|
|
|
// get
|
|
|
|
return mp_obj_new_int(self->tim.Instance->PSC & 0xffff);
|
|
|
|
} else {
|
|
|
|
// set
|
2014-10-04 09:36:39 -04:00
|
|
|
self->tim.Instance->PSC = mp_obj_get_int(args[1]) & 0xffff;
|
2014-04-21 11:48:16 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_prescaler_obj, 1, 2, pyb_timer_prescaler);
|
|
|
|
|
2014-05-02 11:58:15 -04:00
|
|
|
/// \method period([value])
|
|
|
|
/// Get or set the period of the timer.
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_period(size_t n_args, const mp_obj_t *args) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_obj_t *self = MP_OBJ_TO_PTR(args[0]);
|
2014-04-21 11:48:16 -04:00
|
|
|
if (n_args == 1) {
|
|
|
|
// get
|
2018-02-12 23:37:35 -05:00
|
|
|
return mp_obj_new_int(__HAL_TIM_GET_AUTORELOAD(&self->tim) & TIMER_CNT_MASK(self));
|
2014-04-21 11:48:16 -04:00
|
|
|
} else {
|
|
|
|
// set
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_TIM_SET_AUTORELOAD(&self->tim, mp_obj_get_int(args[1]) & TIMER_CNT_MASK(self));
|
2014-04-21 11:48:16 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_period_obj, 1, 2, pyb_timer_period);
|
2014-04-02 10:09:36 -04:00
|
|
|
|
2014-05-02 11:58:15 -04:00
|
|
|
/// \method callback(fun)
|
|
|
|
/// Set the function to be called when the timer triggers.
|
|
|
|
/// `fun` is passed 1 argument, the timer object.
|
|
|
|
/// If `fun` is `None` then the callback will be disabled.
|
2014-04-21 11:48:16 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_callback(mp_obj_t self_in, mp_obj_t callback) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
2014-04-21 11:48:16 -04:00
|
|
|
if (callback == mp_const_none) {
|
|
|
|
// stop interrupt (but not timer)
|
|
|
|
__HAL_TIM_DISABLE_IT(&self->tim, TIM_IT_UPDATE);
|
|
|
|
self->callback = mp_const_none;
|
|
|
|
} else if (mp_obj_is_callable(callback)) {
|
2015-03-10 02:44:26 -04:00
|
|
|
__HAL_TIM_DISABLE_IT(&self->tim, TIM_IT_UPDATE);
|
2014-04-21 11:48:16 -04:00
|
|
|
self->callback = callback;
|
2015-03-10 02:44:26 -04:00
|
|
|
// start timer, so that it interrupts on overflow, but clear any
|
|
|
|
// pending interrupts which may have been set by initializing it.
|
|
|
|
__HAL_TIM_CLEAR_FLAG(&self->tim, TIM_IT_UPDATE);
|
2021-01-26 08:49:56 -05:00
|
|
|
HAL_TIM_Base_Stop(&self->tim); // internal timer state must be released before starting again
|
2015-03-10 02:44:26 -04:00
|
|
|
HAL_TIM_Base_Start_IT(&self->tim); // This will re-enable the IRQ
|
2015-02-22 22:58:51 -05:00
|
|
|
HAL_NVIC_EnableIRQ(self->irqn);
|
2014-04-21 11:48:16 -04:00
|
|
|
} else {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("callback must be None or a callable object"));
|
2014-04-02 10:09:36 -04:00
|
|
|
}
|
2014-04-21 11:48:16 -04:00
|
|
|
return mp_const_none;
|
2014-04-02 10:09:36 -04:00
|
|
|
}
|
2014-04-21 11:48:16 -04:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_timer_callback_obj, pyb_timer_callback);
|
|
|
|
|
2017-05-06 03:03:40 -04:00
|
|
|
STATIC const mp_rom_map_elem_t pyb_timer_locals_dict_table[] = {
|
2014-04-21 11:48:16 -04:00
|
|
|
// instance methods
|
2017-05-06 03:03:40 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&pyb_timer_init_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&pyb_timer_deinit_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_channel), MP_ROM_PTR(&pyb_timer_channel_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_counter), MP_ROM_PTR(&pyb_timer_counter_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_source_freq), MP_ROM_PTR(&pyb_timer_source_freq_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_freq), MP_ROM_PTR(&pyb_timer_freq_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_prescaler), MP_ROM_PTR(&pyb_timer_prescaler_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_period), MP_ROM_PTR(&pyb_timer_period_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_callback), MP_ROM_PTR(&pyb_timer_callback_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_UP), MP_ROM_INT(TIM_COUNTERMODE_UP) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_DOWN), MP_ROM_INT(TIM_COUNTERMODE_DOWN) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_CENTER), MP_ROM_INT(TIM_COUNTERMODE_CENTERALIGNED1) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PWM), MP_ROM_INT(CHANNEL_MODE_PWM_NORMAL) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_PWM_INVERTED), MP_ROM_INT(CHANNEL_MODE_PWM_INVERTED) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_OC_TIMING), MP_ROM_INT(CHANNEL_MODE_OC_TIMING) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_OC_ACTIVE), MP_ROM_INT(CHANNEL_MODE_OC_ACTIVE) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_OC_INACTIVE), MP_ROM_INT(CHANNEL_MODE_OC_INACTIVE) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_OC_TOGGLE), MP_ROM_INT(CHANNEL_MODE_OC_TOGGLE) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_OC_FORCED_ACTIVE), MP_ROM_INT(CHANNEL_MODE_OC_FORCED_ACTIVE) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_OC_FORCED_INACTIVE), MP_ROM_INT(CHANNEL_MODE_OC_FORCED_INACTIVE) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_IC), MP_ROM_INT(CHANNEL_MODE_IC) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_ENC_A), MP_ROM_INT(CHANNEL_MODE_ENC_A) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_ENC_B), MP_ROM_INT(CHANNEL_MODE_ENC_B) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_ENC_AB), MP_ROM_INT(CHANNEL_MODE_ENC_AB) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_HIGH), MP_ROM_INT(TIM_OCPOLARITY_HIGH) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_LOW), MP_ROM_INT(TIM_OCPOLARITY_LOW) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_RISING), MP_ROM_INT(TIM_ICPOLARITY_RISING) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_FALLING), MP_ROM_INT(TIM_ICPOLARITY_FALLING) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_BOTH), MP_ROM_INT(TIM_ICPOLARITY_BOTHEDGE) },
|
2019-03-14 07:15:35 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_BRK_OFF), MP_ROM_INT(BRK_OFF) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_BRK_LOW), MP_ROM_INT(BRK_LOW) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_BRK_HIGH), MP_ROM_INT(BRK_HIGH) },
|
2014-04-21 11:48:16 -04:00
|
|
|
};
|
|
|
|
STATIC MP_DEFINE_CONST_DICT(pyb_timer_locals_dict, pyb_timer_locals_dict_table);
|
|
|
|
|
2021-07-14 00:38:38 -04:00
|
|
|
MP_DEFINE_CONST_OBJ_TYPE(
|
|
|
|
pyb_timer_type,
|
|
|
|
MP_QSTR_Timer,
|
|
|
|
MP_TYPE_FLAG_NONE,
|
2022-09-16 10:31:23 -04:00
|
|
|
make_new, pyb_timer_make_new,
|
2021-07-14 00:38:38 -04:00
|
|
|
print, pyb_timer_print,
|
2022-06-24 02:27:46 -04:00
|
|
|
locals_dict, &pyb_timer_locals_dict
|
2021-07-14 00:38:38 -04:00
|
|
|
);
|
2014-04-21 11:48:16 -04:00
|
|
|
|
2014-08-20 16:21:11 -04:00
|
|
|
/// \moduleref pyb
|
|
|
|
/// \class TimerChannel - setup a channel for a timer.
|
|
|
|
///
|
|
|
|
/// Timer channels are used to generate/capture a signal using a timer.
|
|
|
|
///
|
|
|
|
/// TimerChannel objects are created using the Timer.channel() method.
|
2015-04-09 18:56:15 -04:00
|
|
|
STATIC void pyb_timer_channel_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_channel_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
2014-08-20 16:21:11 -04:00
|
|
|
|
2015-04-09 18:56:15 -04:00
|
|
|
mp_printf(print, "TimerChannel(timer=%u, channel=%u, mode=%s)",
|
2014-08-20 16:21:11 -04:00
|
|
|
self->timer->tim_id,
|
|
|
|
self->channel,
|
2014-09-21 17:54:02 -04:00
|
|
|
qstr_str(channel_mode_info[self->mode].name));
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
|
|
|
|
/// \method capture([value])
|
|
|
|
/// Get or set the capture value associated with a channel.
|
|
|
|
/// capture, compare, and pulse_width are all aliases for the same function.
|
|
|
|
/// capture is the logical name to use when the channel is in input capture mode.
|
|
|
|
|
|
|
|
/// \method compare([value])
|
|
|
|
/// Get or set the compare value associated with a channel.
|
|
|
|
/// capture, compare, and pulse_width are all aliases for the same function.
|
|
|
|
/// compare is the logical name to use when the channel is in output compare mode.
|
|
|
|
|
|
|
|
/// \method pulse_width([value])
|
|
|
|
/// Get or set the pulse width value associated with a channel.
|
|
|
|
/// capture, compare, and pulse_width are all aliases for the same function.
|
|
|
|
/// pulse_width is the logical name to use when the channel is in PWM mode.
|
2014-09-26 12:04:05 -04:00
|
|
|
///
|
|
|
|
/// In edge aligned mode, a pulse_width of `period + 1` corresponds to a duty cycle of 100%
|
|
|
|
/// In center aligned mode, a pulse width of `period` corresponds to a duty cycle of 100%
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_channel_capture_compare(size_t n_args, const mp_obj_t *args) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_channel_obj_t *self = MP_OBJ_TO_PTR(args[0]);
|
2014-08-20 16:21:11 -04:00
|
|
|
if (n_args == 1) {
|
|
|
|
// get
|
2018-02-12 23:37:35 -05:00
|
|
|
return mp_obj_new_int(__HAL_TIM_GET_COMPARE(&self->timer->tim, TIMER_CHANNEL(self)) & TIMER_CNT_MASK(self->timer));
|
2014-08-20 16:21:11 -04:00
|
|
|
} else {
|
|
|
|
// set
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_TIM_SET_COMPARE(&self->timer->tim, TIMER_CHANNEL(self), mp_obj_get_int(args[1]) & TIMER_CNT_MASK(self->timer));
|
2014-08-20 16:21:11 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_channel_capture_compare_obj, 1, 2, pyb_timer_channel_capture_compare);
|
|
|
|
|
2014-09-25 10:44:10 -04:00
|
|
|
/// \method pulse_width_percent([value])
|
|
|
|
/// Get or set the pulse width percentage associated with a channel. The value
|
|
|
|
/// is a number between 0 and 100 and sets the percentage of the timer period
|
|
|
|
/// for which the pulse is active. The value can be an integer or
|
|
|
|
/// floating-point number for more accuracy. For example, a value of 25 gives
|
|
|
|
/// a duty cycle of 25%.
|
2017-08-29 20:59:58 -04:00
|
|
|
STATIC mp_obj_t pyb_timer_channel_pulse_width_percent(size_t n_args, const mp_obj_t *args) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_channel_obj_t *self = MP_OBJ_TO_PTR(args[0]);
|
2014-09-26 12:04:05 -04:00
|
|
|
uint32_t period = compute_period(self->timer);
|
2014-09-21 17:54:02 -04:00
|
|
|
if (n_args == 1) {
|
|
|
|
// get
|
2018-02-12 23:37:35 -05:00
|
|
|
uint32_t cmp = __HAL_TIM_GET_COMPARE(&self->timer->tim, TIMER_CHANNEL(self)) & TIMER_CNT_MASK(self->timer);
|
2014-09-26 12:04:05 -04:00
|
|
|
return compute_percent_from_pwm_value(period, cmp);
|
2014-09-21 17:54:02 -04:00
|
|
|
} else {
|
|
|
|
// set
|
2014-09-25 10:44:10 -04:00
|
|
|
uint32_t cmp = compute_pwm_value_from_percent(period, args[1]);
|
2018-02-12 23:37:35 -05:00
|
|
|
__HAL_TIM_SET_COMPARE(&self->timer->tim, TIMER_CHANNEL(self), cmp & TIMER_CNT_MASK(self->timer));
|
2014-09-21 17:54:02 -04:00
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
}
|
2014-09-22 01:40:42 -04:00
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_channel_pulse_width_percent_obj, 1, 2, pyb_timer_channel_pulse_width_percent);
|
2014-09-21 17:54:02 -04:00
|
|
|
|
2014-08-20 16:21:11 -04:00
|
|
|
/// \method callback(fun)
|
|
|
|
/// Set the function to be called when the timer channel triggers.
|
|
|
|
/// `fun` is passed 1 argument, the timer object.
|
|
|
|
/// If `fun` is `None` then the callback will be disabled.
|
|
|
|
STATIC mp_obj_t pyb_timer_channel_callback(mp_obj_t self_in, mp_obj_t callback) {
|
2018-07-08 09:25:11 -04:00
|
|
|
pyb_timer_channel_obj_t *self = MP_OBJ_TO_PTR(self_in);
|
2014-08-20 16:21:11 -04:00
|
|
|
if (callback == mp_const_none) {
|
|
|
|
// stop interrupt (but not timer)
|
|
|
|
__HAL_TIM_DISABLE_IT(&self->timer->tim, TIMER_IRQ_MASK(self->channel));
|
|
|
|
self->callback = mp_const_none;
|
|
|
|
} else if (mp_obj_is_callable(callback)) {
|
|
|
|
self->callback = callback;
|
2017-04-13 15:38:17 -04:00
|
|
|
__HAL_TIM_CLEAR_IT(&self->timer->tim, TIMER_IRQ_MASK(self->channel));
|
2019-07-05 03:24:59 -04:00
|
|
|
#if defined(TIM1)
|
|
|
|
if (self->timer->tim_id == 1) {
|
2016-08-18 23:47:49 -04:00
|
|
|
HAL_NVIC_EnableIRQ(TIM1_CC_IRQn);
|
2019-07-05 03:24:59 -04:00
|
|
|
} else
|
|
|
|
#endif
|
2016-08-18 23:47:49 -04:00
|
|
|
#if defined(TIM8) // STM32F401 doesn't have a TIM8
|
2019-07-05 03:24:59 -04:00
|
|
|
if (self->timer->tim_id == 8) {
|
2016-08-18 23:47:49 -04:00
|
|
|
HAL_NVIC_EnableIRQ(TIM8_CC_IRQn);
|
2019-07-05 03:24:59 -04:00
|
|
|
} else
|
2016-08-18 23:47:49 -04:00
|
|
|
#endif
|
2019-07-05 03:24:59 -04:00
|
|
|
{
|
2016-08-18 23:47:49 -04:00
|
|
|
HAL_NVIC_EnableIRQ(self->timer->irqn);
|
|
|
|
}
|
2014-08-20 16:21:11 -04:00
|
|
|
// start timer, so that it interrupts on overflow
|
|
|
|
switch (self->mode) {
|
|
|
|
case CHANNEL_MODE_PWM_NORMAL:
|
|
|
|
case CHANNEL_MODE_PWM_INVERTED:
|
2022-09-01 05:08:18 -04:00
|
|
|
HAL_TIM_PWM_Stop_IT(&self->timer->tim, TIMER_CHANNEL(self));
|
2014-08-20 16:21:11 -04:00
|
|
|
HAL_TIM_PWM_Start_IT(&self->timer->tim, TIMER_CHANNEL(self));
|
|
|
|
break;
|
|
|
|
case CHANNEL_MODE_OC_TIMING:
|
|
|
|
case CHANNEL_MODE_OC_ACTIVE:
|
|
|
|
case CHANNEL_MODE_OC_INACTIVE:
|
|
|
|
case CHANNEL_MODE_OC_TOGGLE:
|
|
|
|
case CHANNEL_MODE_OC_FORCED_ACTIVE:
|
|
|
|
case CHANNEL_MODE_OC_FORCED_INACTIVE:
|
2022-09-01 05:08:18 -04:00
|
|
|
HAL_TIM_OC_Stop_IT(&self->timer->tim, TIMER_CHANNEL(self));
|
2014-08-20 16:21:11 -04:00
|
|
|
HAL_TIM_OC_Start_IT(&self->timer->tim, TIMER_CHANNEL(self));
|
|
|
|
break;
|
|
|
|
case CHANNEL_MODE_IC:
|
2022-09-01 05:08:18 -04:00
|
|
|
HAL_TIM_IC_Stop_IT(&self->timer->tim, TIMER_CHANNEL(self));
|
2014-08-20 16:21:11 -04:00
|
|
|
HAL_TIM_IC_Start_IT(&self->timer->tim, TIMER_CHANNEL(self));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
} else {
|
2020-03-02 06:35:22 -05:00
|
|
|
mp_raise_ValueError(MP_ERROR_TEXT("callback must be None or a callable object"));
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
return mp_const_none;
|
|
|
|
}
|
|
|
|
STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_timer_channel_callback_obj, pyb_timer_channel_callback);
|
|
|
|
|
2017-05-06 03:03:40 -04:00
|
|
|
STATIC const mp_rom_map_elem_t pyb_timer_channel_locals_dict_table[] = {
|
2014-08-20 16:21:11 -04:00
|
|
|
// instance methods
|
2017-05-06 03:03:40 -04:00
|
|
|
{ MP_ROM_QSTR(MP_QSTR_callback), MP_ROM_PTR(&pyb_timer_channel_callback_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_pulse_width), MP_ROM_PTR(&pyb_timer_channel_capture_compare_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_pulse_width_percent), MP_ROM_PTR(&pyb_timer_channel_pulse_width_percent_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_capture), MP_ROM_PTR(&pyb_timer_channel_capture_compare_obj) },
|
|
|
|
{ MP_ROM_QSTR(MP_QSTR_compare), MP_ROM_PTR(&pyb_timer_channel_capture_compare_obj) },
|
2014-08-20 16:21:11 -04:00
|
|
|
};
|
|
|
|
STATIC MP_DEFINE_CONST_DICT(pyb_timer_channel_locals_dict, pyb_timer_channel_locals_dict_table);
|
|
|
|
|
2021-07-14 00:38:38 -04:00
|
|
|
STATIC MP_DEFINE_CONST_OBJ_TYPE(
|
|
|
|
pyb_timer_channel_type,
|
|
|
|
MP_QSTR_TimerChannel,
|
|
|
|
MP_TYPE_FLAG_NONE,
|
|
|
|
print, pyb_timer_channel_print,
|
2022-06-24 02:27:46 -04:00
|
|
|
locals_dict, &pyb_timer_channel_locals_dict
|
2021-07-14 00:38:38 -04:00
|
|
|
);
|
2014-08-20 16:21:11 -04:00
|
|
|
|
2014-09-21 17:54:02 -04:00
|
|
|
STATIC void timer_handle_irq_channel(pyb_timer_obj_t *tim, uint8_t channel, mp_obj_t callback) {
|
2014-08-20 16:21:11 -04:00
|
|
|
uint32_t irq_mask = TIMER_IRQ_MASK(channel);
|
|
|
|
|
|
|
|
if (__HAL_TIM_GET_FLAG(&tim->tim, irq_mask) != RESET) {
|
2018-02-12 23:37:35 -05:00
|
|
|
if (__HAL_TIM_GET_IT_SOURCE(&tim->tim, irq_mask) != RESET) {
|
2014-08-20 16:21:11 -04:00
|
|
|
// clear the interrupt
|
|
|
|
__HAL_TIM_CLEAR_IT(&tim->tim, irq_mask);
|
|
|
|
|
|
|
|
// execute callback if it's set
|
|
|
|
if (callback != mp_const_none) {
|
2017-02-15 07:04:53 -05:00
|
|
|
mp_sched_lock();
|
2014-08-20 16:21:11 -04:00
|
|
|
// When executing code within a handler we must lock the GC to prevent
|
|
|
|
// any memory allocations. We must also catch any exceptions.
|
|
|
|
gc_lock();
|
|
|
|
nlr_buf_t nlr;
|
|
|
|
if (nlr_push(&nlr) == 0) {
|
2018-07-08 09:25:11 -04:00
|
|
|
mp_call_function_1(callback, MP_OBJ_FROM_PTR(tim));
|
2014-08-20 16:21:11 -04:00
|
|
|
nlr_pop();
|
|
|
|
} else {
|
|
|
|
// Uncaught exception; disable the callback so it doesn't run again.
|
|
|
|
tim->callback = mp_const_none;
|
|
|
|
__HAL_TIM_DISABLE_IT(&tim->tim, irq_mask);
|
|
|
|
if (channel == 0) {
|
2019-09-23 03:15:07 -04:00
|
|
|
mp_printf(MICROPY_ERROR_PRINTER, "uncaught exception in Timer(%u) interrupt handler\n", tim->tim_id);
|
2014-08-20 16:21:11 -04:00
|
|
|
} else {
|
2019-09-23 03:15:07 -04:00
|
|
|
mp_printf(MICROPY_ERROR_PRINTER, "uncaught exception in Timer(%u) channel %u interrupt handler\n", tim->tim_id, channel);
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
2018-07-08 09:25:11 -04:00
|
|
|
mp_obj_print_exception(&mp_plat_print, MP_OBJ_FROM_PTR(nlr.ret_val));
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
gc_unlock();
|
2017-02-15 07:04:53 -05:00
|
|
|
mp_sched_unlock();
|
2014-08-20 16:21:11 -04:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-04-21 11:48:16 -04:00
|
|
|
void timer_irq_handler(uint tim_id) {
|
|
|
|
if (tim_id - 1 < PYB_TIMER_OBJ_ALL_NUM) {
|
|
|
|
// get the timer object
|
2015-01-07 18:38:50 -05:00
|
|
|
pyb_timer_obj_t *tim = MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1];
|
2014-04-21 11:48:16 -04:00
|
|
|
|
|
|
|
if (tim == NULL) {
|
2014-09-21 17:54:02 -04:00
|
|
|
// Timer object has not been set, so we can't do anything.
|
|
|
|
// This can happen under normal circumstances for timers like
|
|
|
|
// 1 & 10 which use the same IRQ.
|
2014-04-21 11:48:16 -04:00
|
|
|
return;
|
|
|
|
}
|
2014-04-02 10:09:36 -04:00
|
|
|
|
2014-08-20 16:21:11 -04:00
|
|
|
// Check for timer (versus timer channel) interrupt.
|
|
|
|
timer_handle_irq_channel(tim, 0, tim->callback);
|
|
|
|
uint32_t handled = TIMER_IRQ_MASK(0);
|
|
|
|
|
|
|
|
// Check to see if a timer channel interrupt was pending
|
|
|
|
pyb_timer_channel_obj_t *chan = tim->channel;
|
|
|
|
while (chan != NULL) {
|
|
|
|
timer_handle_irq_channel(tim, chan->channel, chan->callback);
|
|
|
|
handled |= TIMER_IRQ_MASK(chan->channel);
|
|
|
|
chan = chan->next;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Finally, clear any remaining interrupt sources. Otherwise we'll
|
|
|
|
// just get called continuously.
|
2015-03-10 02:44:26 -04:00
|
|
|
uint32_t unhandled = tim->tim.Instance->DIER & 0xff & ~handled;
|
2014-08-20 16:21:11 -04:00
|
|
|
if (unhandled != 0) {
|
2015-04-28 03:17:05 -04:00
|
|
|
__HAL_TIM_DISABLE_IT(&tim->tim, unhandled);
|
2014-08-20 16:21:11 -04:00
|
|
|
__HAL_TIM_CLEAR_IT(&tim->tim, unhandled);
|
2019-09-23 03:15:07 -04:00
|
|
|
mp_printf(MICROPY_ERROR_PRINTER, "unhandled interrupt SR=0x%02x (now disabled)\n", (unsigned int)unhandled);
|
2014-04-21 11:48:16 -04:00
|
|
|
}
|
2014-04-02 10:09:36 -04:00
|
|
|
}
|
|
|
|
}
|
2022-07-01 15:48:59 -04:00
|
|
|
|
|
|
|
MP_REGISTER_ROOT_POINTER(struct _pyb_timer_obj_t *pyb_timer_obj_all[MICROPY_HW_MAX_TIMER]);
|