765 lines
41 KiB
C
765 lines
41 KiB
C
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//*****************************************************************************
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//
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// Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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//
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//*****************************************************************************
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#ifndef __HW_STACK_DIE_CTRL_H__
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#define __HW_STACK_DIE_CTRL_H__
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//*****************************************************************************
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//
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// The following are defines for the STACK_DIE_CTRL register offsets.
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//
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//*****************************************************************************
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#define STACK_DIE_CTRL_O_STK_UP_RESET \
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0x00000000 // Can be written only by Base
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// Processor. Writing to this
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// register will reset the stack
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// processor reset will be
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// de-asserted upon clearing this
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// register.
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#define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \
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0x00000004 // This register defines who among
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// base processor and stack
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// processor have highest priority
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// for Sram Access. Can be written
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// only by Base Processor.
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#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \
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0x00000008 // In Spinlock mode this Register
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// defines who among base processor
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// and stack processor have access
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// to Sram Bank2 right now. In
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// Handshake mode this Register
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// defines who among base processor
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// and stack processor have access
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// to Sram Bank2 and Bank3 right
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// now. Its Clear only register and
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// is set by hardware. Lower bit can
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// be cleared only by Base Processor
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// and Upper bit Cleared only by the
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// Stack processor.
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#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \
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0x0000000C // In Spinlock mode whenever Base
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// processor wants the access to
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// Sram Bank2 it should request for
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// it by writing into this register.
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// It'll get interrupt whenever it
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// is granted. In Handshake mode
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// this bit will be set by Stack
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// processor. Its a set only bit and
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// is cleared by HW when the request
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// is granted.
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#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \
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0x00000010 // In Spinlock mode Whenever Stack
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// processor wants the access to
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// Sram Bank2 it should request for
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// it by writing into this register.
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// It'll get interrupt whenever it
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// is granted. In Handshake mode
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// this bit will be set by the Base
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// processor. Its a set only bit and
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// is cleared by HW when the request
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// is granted.
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#define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \
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0x00000014 // Register defines who among base
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// processor and stack processor
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// have access to Sram Bank3 right
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// now. Its Clear only register and
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// is set by hardware. Lower bit can
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// be cleared only by Base Processor
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// and Upper bit Cleared only by the
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// Stack processor.
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#define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \
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0x00000018 // In Spinlock mode whenever Base
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// processor wants the access to
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// Sram Bank3 it should request for
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// it by writing into this register.
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// It'll get interrupt whenever it
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// is granted. In Handshake mode
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// this bit will be set by Stack
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// processor. Its a set only bit and
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// is cleared by HW when the request
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// is granted.
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#define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \
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0x0000001C // In Spinlock mode Whenever Stack
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// processor wants the access to
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// Sram Bank3 it should request for
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// it by writing into this register.
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// It'll get interrupt whenever it
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// is granted. In Handshake mode
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// this bit will be set by the Base
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// processor. Its a set only bit and
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// is cleared by HW when the request
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// is granted.
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#define STACK_DIE_CTRL_O_RDSM_CFG_CPU \
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0x00000020 // Read State Machine timing
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// configuration register. Generally
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// Bit 4 and 3 will be identical.
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// For stacked die always 43 are 0
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// and 6:5 == 1 for 120Mhz.
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#define STACK_DIE_CTRL_O_RDSM_CFG_EE \
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0x00000024 // Read State Machine timing
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// configuration register. Generally
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// Bit 4 and 3 will be identical.
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// For stacked die always 43 are 0
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// and 6:5 == 1 for 120Mhz.
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#define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \
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0x00000028 // Reading this register Base
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// procesor will able to know the
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// reason for the interrupt. This is
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// clear only register - set by HW
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// upon an interrupt to Base
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// processor and can be cleared only
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// by BASE processor.
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#define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \
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0x0000002C // Reading this register Stack
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// procesor will able to know the
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// reason for the interrupt. This is
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// clear only register - set by HW
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// upon an interrupt to Stack
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// processor and can be cleared only
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// by Stack processor.
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#define STACK_DIE_CTRL_O_STK_CLK_EN \
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0x00000030 // Can be written only by base
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// processor. Controls the enable
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// pin of the cgcs for the clocks
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// going to CM3 dft ctrl block and
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// Sram.
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#define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \
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0x00000034 // Can be written only by the base
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// processor. Decides the ram
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// sharing mode :: handshake or
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// Spinlock mode.
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#define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \
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0x00000038 // Stores the last bus fault
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// address.
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#define STACK_DIE_CTRL_O_BUS_FAULT_CLR \
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0x0000003C // write only registers on read
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// returns 0.W Write 1 to clear the
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// bust fault to store the new bus
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// fault address
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#define STACK_DIE_CTRL_O_RESET_CAUSE \
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0x00000040 // Reset cause value captured from
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// the ICR_CLKRST block.
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#define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \
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0x00000044 // Watchdog timer event value
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// captured from the ICR_CLKRST
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// block
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#define STACK_DIE_CTRL_O_DMA_REQ \
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0x00000048 // To send Dma Request to bottom
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// die.
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#define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \
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0x0000004C // Address offset within SRAM to
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// which CM3 should jump after
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// reset.
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#define STACK_DIE_CTRL_O_SW_REG1 \
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0x00000050 // These are sw registers for
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// topdie processor and bottom die
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// processor to communicate. Both
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// can set and read these registers.
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// In case of write clash bottom
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// die's processor wins and top die
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// processor access is ignored.
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#define STACK_DIE_CTRL_O_SW_REG2 \
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0x00000054 // These are sw registers for
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// topdie processor and bottom die
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// processor to communicate. Both
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// can set and read these registers.
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// In case of write clash bottom
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// die's processor wins and top die
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// processor access is ignored.
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#define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \
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0x00000058 // By posting the request Flash can
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// be put into low-power mode
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// (Sleep) without powering down the
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// Flash. Earlier (in Garnet) this
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// was fully h/w controlled and the
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// control for this was coming from
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// SysCtl while entering into Cortex
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// Deep-sleep mode. But for our
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// device the D2D i/f doesnt support
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// this. The Firmware has to program
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// the register in the top-die for
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// entering into this mode and wait
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// for an interrupt.
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#define STACK_DIE_CTRL_O_MISC_CTL \
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0x0000005C // Miscellanious control register.
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#define STACK_DIE_CTRL_O_SW_DFT_CTL \
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0x000000FC // DFT control and status bits
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#define STACK_DIE_CTRL_O_PADN_CTL_0 \
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0x00000100 // Mainly for For controlling the
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// pads OEN pins. There are total 60
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// pads and hence 60 control registe
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// i.e n value varies from 0 to 59.
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// Here is the mapping for the
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// pad_ctl register number and the
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// functionality : 0 D2DPAD_DMAREQ1
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// 1 D2DPAD_DMAREQ0 2
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// D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4
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// D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6
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// D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8
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// D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS
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// 10 D2DPAD_JTAG_TDI 11-27
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// D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE
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// -1:0] 28-56 D2DPAD_TOSTACK
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// [D2D_TOSTACK_SIZE -1:0] 57-59
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// D2DPAD_SPARE [D2D_SPARE_PAD_SIZE
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// -1:0] 0:00
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// STACK_DIE_CTRL_O_STK_UP_RESET register.
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//
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//******************************************************************************
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#define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \
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0x00000001 // 1 :Assert Reset 0 : Deassert the
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// Reset
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register.
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//
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//******************************************************************************
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#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \
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0x00000003 // 00 : Equal Priority 01 : Stack
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// Processor have priority 10 : Base
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// Processor have priority 11 :
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// Unused
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#define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register.
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//
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//******************************************************************************
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#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \
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0x00000002 // Stack Processor should clear it
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// when it is done with the sram
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// bank usage. Set by HW It is set
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// when Stack Processor is granted
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// the access to this bank
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#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \
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0x00000001 // Base Processor should clear it
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// when it is done wth the sram
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// usage. Set by HW It is set when
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// Base Processor is granted the
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// access to this bank
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register.
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//
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//******************************************************************************
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#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \
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0x00000001 // Base Processor will set when
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// Sram access is needed in Spin
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// Lock mode. In Handshake mode
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// Stack Processor will set to
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// inform Base Processor that it is
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// done with the processing of data
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// in SRAM and is now ready to use
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// by the base processor.
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register.
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//
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//******************************************************************************
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#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \
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0x00000001 // Stack Processor will set when
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// Sram access is needed in Spin
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// Lock mode. In Handshake mode Base
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// Processor will set to inform
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// Stack Processor to start
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// processing the data in the Ram.
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register.
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//
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//******************************************************************************
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#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \
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0x00000002 // Stack Processor should clear it
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// when it is done with the sram
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// bank usage. Set by HW It is set
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// when Stack Processor is granted
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// the access to this bank.
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#define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \
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0x00000001 // Base Processor should clear it
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// when it is done wth the sram
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// usage. Set by HW it is set when
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// Base Processor is granted the
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// access to this bank.
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \
|
||
|
|
0x00000001 // Base Processor will set when
|
||
|
|
// Sram access is needed in Spin
|
||
|
|
// Lock mode. Not used in handshake
|
||
|
|
// mode.
|
||
|
|
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \
|
||
|
|
0x00000001 // Stack Processor will set when
|
||
|
|
// Sram access is needed in Spin
|
||
|
|
// Lock mode.
|
||
|
|
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_RDSM_CFG_CPU register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \
|
||
|
|
0x000000C0 // Bank Clock Hi Time 00 : HCLK
|
||
|
|
// pulse 01 : 1 cycle of HCLK 10 :
|
||
|
|
// 1.5 cycles of HCLK 11 : 2 cycles
|
||
|
|
// of HCLK
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \
|
||
|
|
0x00000020 // FLCLK 0 : indicates flash clock
|
||
|
|
// rise aligns on HCLK rise 1 :
|
||
|
|
// indicates flash clock rise aligns
|
||
|
|
// on HCLK fall
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \
|
||
|
|
0x00000010 // 0 : Always register flash rdata
|
||
|
|
// before sending to CPU 1 : Drive
|
||
|
|
// Flash rdata directly out on MISS
|
||
|
|
// (Both ICODE / DCODE)
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \
|
||
|
|
0x0000000F // Number of wait states inserted
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_RDSM_CFG_EE register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \
|
||
|
|
0x000000C0 // Bank Clock Hi Time 00 : HCLK
|
||
|
|
// pulse 01 : 1 cycle of HCLK 10 :
|
||
|
|
// 1.5 cycles of HCLK 11 : 2 cycles
|
||
|
|
// of HCLK
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \
|
||
|
|
0x00000020 // FLCLK 0 : indicates flash clock
|
||
|
|
// rise aligns on HCLK rise 1 :
|
||
|
|
// indicates flash clock rise aligns
|
||
|
|
// on HCLK fall
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \
|
||
|
|
0x00000010 // 0 : Always register flash rdata
|
||
|
|
// before sending to CPU 1 : Drive
|
||
|
|
// Flash rdata directly out on MISS
|
||
|
|
// (Both ICODE / DCODE)
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \
|
||
|
|
0x0000000F // Number of wait states inserted
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \
|
||
|
|
0x00000010 // Set when Relinquish Interrupt
|
||
|
|
// sent to Base processor for Bank3.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \
|
||
|
|
0x00000008 // Set when Relinquish Interrupt
|
||
|
|
// sent to Base processor for Bank2.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \
|
||
|
|
0x00000004 // Set when Bank3 is granted to
|
||
|
|
// Base processor.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \
|
||
|
|
0x00000002 // Set when Bank2 is granted to
|
||
|
|
// BAse processor.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \
|
||
|
|
0x00000001 // Set when there Base processor do
|
||
|
|
// an Invalid access to Sram. Ex :
|
||
|
|
// Accessing the bank which is not
|
||
|
|
// granted for BAse processor.
|
||
|
|
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \
|
||
|
|
0x00000008 // Set when Relinquish Interrupt
|
||
|
|
// sent to Stack processor for
|
||
|
|
// Bank3.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \
|
||
|
|
0x00000004 // Set when Relinquish Interrupt
|
||
|
|
// sent to Stack processor for
|
||
|
|
// Bank2.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \
|
||
|
|
0x00000002 // Set when Bank3 is granted to
|
||
|
|
// Stack processor.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \
|
||
|
|
0x00000001 // Set when Bank2 is granted to
|
||
|
|
// Stack processor.
|
||
|
|
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_STK_CLK_EN register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \
|
||
|
|
0x00000004 // Enable the clock going to sram.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \
|
||
|
|
0x00000002 // Enable the clock going to dft
|
||
|
|
// control block
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \
|
||
|
|
0x00000001 // Enable the clock going to Cm3
|
||
|
|
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_SPIN_LOCK_MODE register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \
|
||
|
|
0x00000001 // 0 : Handshake Mode 1 : Spinlock
|
||
|
|
// mode.
|
||
|
|
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_BUS_FAULT_ADDR register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \
|
||
|
|
0xFFFFFFFF // Fault Address
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_BUS_FAULT_CLR register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \
|
||
|
|
0x00000001 // When set it'll clear the bust
|
||
|
|
// fault address register to store
|
||
|
|
// the new bus fault address
|
||
|
|
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_RESET_CAUSE register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \
|
||
|
|
0xFFFFFFFF
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \
|
||
|
|
0xFFFFFFFF
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_DMA_REQ register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \
|
||
|
|
0x00000002 // Generate DMAREQ1 on setting this
|
||
|
|
// bit.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \
|
||
|
|
0x00000001 // Generate DMAREQ0 on setting this
|
||
|
|
// bit.
|
||
|
|
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \
|
||
|
|
0xFFFFFFFF
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_SW_REG1 register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \
|
||
|
|
0xFFFFFFFF
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_SW_REG2 register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \
|
||
|
|
0xFFFFFFFF
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_FMC_SLEEP_CTL register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \
|
||
|
|
0x00000002 // captures the status of of
|
||
|
|
// fmc_lpm_ack
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \
|
||
|
|
0x00000001 // When set assert
|
||
|
|
// iflpe2fmc_lpm_req to FMC.
|
||
|
|
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_MISC_CTL register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \
|
||
|
|
0x00000080 // 1 : will reset the async wdog
|
||
|
|
// timer runing on piosc clock
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \
|
||
|
|
0x00000020 // Setting this Will send to
|
||
|
|
// interttupt to CM3
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \
|
||
|
|
0x00000010 // Setting this Will send to
|
||
|
|
// interttupt to CM3
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \
|
||
|
|
0x00000008 // Setting this Will send to
|
||
|
|
// interttupt to CM3
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \
|
||
|
|
0x00000004 // While testing Flash Setting this
|
||
|
|
// bit will Control the
|
||
|
|
// CE/STR/AIN/CLKIN going to flash
|
||
|
|
// banks 12 and 3. 0 : Control
|
||
|
|
// signals coming from FMC for Bank
|
||
|
|
// 3 goes to Bank3 1 : Control
|
||
|
|
// signals coming from FMC for Bank
|
||
|
|
// 0 goes to Bank2
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \
|
||
|
|
0x00000002 // While testing Flash Setting this
|
||
|
|
// bit will Control the
|
||
|
|
// CE/STR/AIN/CLKIN going to flash
|
||
|
|
// banks 12 and 3. 0 : Control
|
||
|
|
// signals coming from FMC for Bank
|
||
|
|
// 2 goes to Bank2 1 : Control
|
||
|
|
// signals coming from FMC for Bank
|
||
|
|
// 0 goes to Bank2
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \
|
||
|
|
0x00000001 // While testing Flash Setting this
|
||
|
|
// bit will Control the
|
||
|
|
// CE/STR/AIN/CLKIN going to flash
|
||
|
|
// banks 12 and 3. 0 : Control
|
||
|
|
// signals coming from FMC for Bank
|
||
|
|
// 1 goes to Bank1 1 : Control
|
||
|
|
// signals coming from FMC for Bank
|
||
|
|
// 0 goes to Bank1
|
||
|
|
|
||
|
|
//******************************************************************************
|
||
|
|
//
|
||
|
|
// The following are defines for the bit fields in the
|
||
|
|
// STACK_DIE_CTRL_O_SW_DFT_CTL register.
|
||
|
|
//
|
||
|
|
//******************************************************************************
|
||
|
|
#define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \
|
||
|
|
0x20000000 // when set to '1' all flash
|
||
|
|
// control signals switch over to
|
||
|
|
// CM3 control when '0' it is under
|
||
|
|
// the D2D interface control
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \
|
||
|
|
0x10000000 // 1 indicates in SWIF mode the
|
||
|
|
// control signals to flash are from
|
||
|
|
// FMC CPU read controls the clock
|
||
|
|
// and address. that is one can give
|
||
|
|
// address via FMC and read through
|
||
|
|
// IDMEM.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \
|
||
|
|
0x00800000 // 'CPU Done' bit for PBIST. Write
|
||
|
|
// '1' to indicate test done.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \
|
||
|
|
0x00400000 // 'CPU Fail' bit for PBIST. Write
|
||
|
|
// '1' to indicate test failed.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \
|
||
|
|
0x00001000 // when set to '1' flash bank 4
|
||
|
|
// (EEPROM) is owned by the CM3for
|
||
|
|
// reads over DCODE bus. When '0'
|
||
|
|
// access control given to D2D
|
||
|
|
// interface.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \
|
||
|
|
0x00000800 // when set to '1' flash bank 3 is
|
||
|
|
// owned by the CM3for reads over
|
||
|
|
// DCODE bus. When '0' access
|
||
|
|
// control given to D2D interface.
|
||
|
|
|
||
|
|
#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \
|
||
|
|
0x00000400 // when set to '1' flash bank 2 is
|
||
|
|
// owned by the CM3for reads over
|
||
|
|
// DCODE bus. When '0' access
|
||
|
|
// control given to D2D interface.
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#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \
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0x00000200 // when set to '1' flash bank 1 is
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// owned by the CM3for reads over
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// DCODE bus. When '0' access
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// control given to D2D interface.
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#define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \
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0x00000100 // when set to '1' flash bank 0 is
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// owned by the CM3 for reads over
|
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// DCODE bus. When '0' access
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// control given to D2D interface.
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//******************************************************************************
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//
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// The following are defines for the bit fields in the
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// STACK_DIE_CTRL_O_PADN_CTL_0 register.
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//
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//******************************************************************************
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#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \
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0x00000008 // This bit is valid for only the
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// spare pads ie for n=57 to 59.
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// value to drive at the output of
|
||
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// the pad
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#define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \
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0x00000004 // This bit is valid for only the
|
||
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// spare pads ie for n=57 to 59.
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||
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// captures the 'Y' pin of the pad
|
||
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// which is the data being driven
|
||
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// into the die
|
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#define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \
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0x00000002 // OEN2X control when '1' enables
|
||
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// the output with 1x. Total drive
|
||
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// strength is decided bu oen1x
|
||
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// setting + oen2x setting.
|
||
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|
||
|
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#define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \
|
||
|
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0x00000001 // OEN1X control when '1' enables
|
||
|
|
// the output with 1x . Total drive
|
||
|
|
// strength is decided bu oen1x
|
||
|
|
// setting + oen2x setting.
|
||
|
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||
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||
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||
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#endif // __HW_STACK_DIE_CTRL_H__
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