2014-11-27 15:30:33 -05:00
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/* GNU linker script for ESP8266 */
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MEMORY
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{
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dport0_0_seg : org = 0x3ff00000, len = 0x10
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dram0_0_seg : org = 0x3ffe8000, len = 0x14000
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iram1_0_seg : org = 0x40100000, len = 0x8000
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2015-05-11 09:05:59 -04:00
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irom0_0_seg : org = 0x40210000, len = 0x5A000
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2014-11-27 15:30:33 -05:00
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}
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/* define the top of RAM */
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_heap_end = ORIGIN(dram0_0_seg) + LENGTH(dram0_0_seg);
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PHDRS
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{
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dport0_0_phdr PT_LOAD;
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dram0_0_phdr PT_LOAD;
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dram0_0_bss_phdr PT_LOAD;
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iram1_0_phdr PT_LOAD;
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irom0_0_phdr PT_LOAD;
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}
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ENTRY(call_user_start)
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2015-05-26 12:54:55 -04:00
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EXTERN(_DebugExceptionVector)
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EXTERN(_DoubleExceptionVector)
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EXTERN(_KernelExceptionVector)
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EXTERN(_NMIExceptionVector)
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EXTERN(_UserExceptionVector)
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2014-11-27 15:30:33 -05:00
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PROVIDE(_memmap_vecbase_reset = 0x40000000);
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/* Various memory-map dependent cache attribute settings: */
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_memmap_cacheattr_wb_base = 0x00000110;
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_memmap_cacheattr_wt_base = 0x00000110;
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_memmap_cacheattr_bp_base = 0x00000220;
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_memmap_cacheattr_unused_mask = 0xFFFFF00F;
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_memmap_cacheattr_wb_trapnull = 0x2222211F;
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_memmap_cacheattr_wba_trapnull = 0x2222211F;
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_memmap_cacheattr_wbna_trapnull = 0x2222211F;
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_memmap_cacheattr_wt_trapnull = 0x2222211F;
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_memmap_cacheattr_bp_trapnull = 0x2222222F;
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_memmap_cacheattr_wb_strict = 0xFFFFF11F;
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_memmap_cacheattr_wt_strict = 0xFFFFF11F;
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_memmap_cacheattr_bp_strict = 0xFFFFF22F;
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_memmap_cacheattr_wb_allvalid = 0x22222112;
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_memmap_cacheattr_wt_allvalid = 0x22222112;
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_memmap_cacheattr_bp_allvalid = 0x22222222;
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PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
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SECTIONS
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{
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.dport0.rodata : ALIGN(4)
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{
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_dport0_rodata_start = ABSOLUTE(.);
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*(.dport0.rodata)
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*(.dport.rodata)
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_dport0_rodata_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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2014-11-28 09:58:25 -05:00
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2014-11-27 15:30:33 -05:00
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.dport0.literal : ALIGN(4)
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{
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_dport0_literal_start = ABSOLUTE(.);
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*(.dport0.literal)
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*(.dport.literal)
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_dport0_literal_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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2014-11-28 09:58:25 -05:00
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2014-11-27 15:30:33 -05:00
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.dport0.data : ALIGN(4)
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{
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_dport0_data_start = ABSOLUTE(.);
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*(.dport0.data)
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*(.dport.data)
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_dport0_data_end = ABSOLUTE(.);
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} >dport0_0_seg :dport0_0_phdr
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2014-11-28 09:58:25 -05:00
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.irom0.text : ALIGN(4)
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{
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_irom0_text_start = ABSOLUTE(.);
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*(.irom0.literal .irom.literal .irom.text.literal .irom0.text .irom.text)
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2014-11-29 09:36:18 -05:00
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/* we put some specific text in this section */
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*py/*.o*(.literal* .text*)
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2015-12-18 16:07:58 -05:00
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*lib/libm/*.o*(.literal*, .text*)
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2014-11-29 09:36:18 -05:00
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*pyexec.o(.literal*, .text*)
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*readline.o(.literal*, .text*)
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*pybstdio.o(.literal*, .text*)
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*gccollect.o(.literal* .text*)
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*gchelper.o(.literal* .text*)
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2015-05-13 09:49:14 -04:00
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*modpyb.o(.literal*, .text*)
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*modpybpin.o(.literal*, .text*)
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*modpybrtc.o(.literal*, .text*)
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2015-05-11 09:05:59 -04:00
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*modesp.o(.literal* .text*)
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2015-10-20 17:59:31 -04:00
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*modnetwork.o(.literal* .text*)
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*moduos.o(.literal* .text*)
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2015-05-13 09:49:14 -04:00
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*modutime.o(.literal* .text*)
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2015-12-28 05:23:30 -05:00
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*modlwip.o(.literal* .text*)
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2014-11-29 09:36:18 -05:00
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/* we put as much rodata as possible in this section */
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/* note that only rodata accessed as a machine word is allowed here */
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*py/qstr.o(.rodata.const_pool)
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*py/*.o(.rodata.mp_type_*) /* catches type: mp_obj_type_t */
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*py/*.o(.rodata.*_locals_dict*) /* catches types: mp_obj_dict_t, mp_map_elem_t */
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*py/*.o(.rodata.mp_module_*) /* catches types: mp_obj_module_t, mp_obj_dict_t, mp_map_elem_t */
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2014-11-28 09:58:25 -05:00
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_irom0_text_end = ABSOLUTE(.);
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} >irom0_0_seg :irom0_0_phdr
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.text : ALIGN(4)
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{
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_stext = .;
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_text_start = ABSOLUTE(.);
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2015-05-26 12:54:55 -04:00
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*(.UserEnter.text)
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. = ALIGN(16);
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*(.DebugExceptionVector.text)
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. = ALIGN(16);
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*(.NMIExceptionVector.text)
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. = ALIGN(16);
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*(.KernelExceptionVector.text)
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LONG(0)
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LONG(0)
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LONG(0)
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LONG(0)
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. = ALIGN(16);
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*(.UserExceptionVector.text)
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LONG(0)
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LONG(0)
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LONG(0)
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LONG(0)
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. = ALIGN(16);
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*(.DoubleExceptionVector.text)
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LONG(0)
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LONG(0)
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LONG(0)
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LONG(0)
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. = ALIGN (16);
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2014-11-28 09:58:25 -05:00
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*(.entry.text)
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*(.init.literal)
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*(.init)
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*(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
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*(.fini.literal)
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*(.fini)
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*(.gnu.version)
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_text_end = ABSOLUTE(.);
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_etext = .;
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} >iram1_0_seg :iram1_0_phdr
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.lit4 : ALIGN(4)
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{
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_lit4_start = ABSOLUTE(.);
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*(*.lit4)
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*(.lit4.*)
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*(.gnu.linkonce.lit4.*)
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_lit4_end = ABSOLUTE(.);
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} >iram1_0_seg :iram1_0_phdr
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2014-11-27 15:30:33 -05:00
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.data : ALIGN(4)
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{
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_data_start = ABSOLUTE(.);
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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*(.data1)
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.sdata2)
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*(.sdata2.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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_data_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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2014-11-28 09:58:25 -05:00
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2014-11-27 15:30:33 -05:00
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.rodata : ALIGN(4)
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{
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_rodata_start = ABSOLUTE(.);
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2015-12-27 11:23:11 -05:00
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*(.sdk.version)
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2014-11-27 15:30:33 -05:00
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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__XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
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*(.xt_except_table)
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*(.gcc_except_table)
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*(.gnu.linkonce.e.*)
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*(.gnu.version_r)
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*(.eh_frame)
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/* C++ constructor and destructor tables, properly ordered: */
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KEEP (*crtbegin.o(.ctors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
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KEEP (*(SORT(.ctors.*)))
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KEEP (*(.ctors))
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KEEP (*crtbegin.o(.dtors))
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KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
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KEEP (*(SORT(.dtors.*)))
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KEEP (*(.dtors))
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/* C++ exception handlers table: */
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__XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
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*(.xt_except_desc)
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*(.gnu.linkonce.h.*)
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__XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
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*(.xt_except_desc_end)
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*(.dynamic)
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*(.gnu.version_d)
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. = ALIGN(4); /* this table MUST be 4-byte aligned */
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_bss_table_start = ABSOLUTE(.);
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LONG(_bss_start)
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LONG(_bss_end)
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_bss_table_end = ABSOLUTE(.);
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_rodata_end = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_phdr
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2014-11-28 09:58:25 -05:00
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2014-11-27 15:30:33 -05:00
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.bss ALIGN(8) (NOLOAD) : ALIGN(4)
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{
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. = ALIGN (8);
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_bss_start = ABSOLUTE(.);
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*(.dynsbss)
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*(.sbss)
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*(.sbss.*)
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*(.gnu.linkonce.sb.*)
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*(.scommon)
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*(.sbss2)
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*(.sbss2.*)
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*(.gnu.linkonce.sb2.*)
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*(.dynbss)
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*(.bss)
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*(.bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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. = ALIGN (8);
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_bss_end = ABSOLUTE(.);
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_heap_start = ABSOLUTE(.);
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} >dram0_0_seg :dram0_0_bss_phdr
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}
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/* get ROM code address */
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INCLUDE "eagle.rom.addr.v6.ld"
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